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bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-1 product overview S3C24A0 an application processor for 2.5g/3g mobile phones soc r&d center samsung electronics corp.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-2 contents ch1. introduction ch2. srom ch3. sdram ch4. nand ch5. bus matrix ch6. interrupt ch7. pwm timer ch8. watch dog timer ch9. dma ch10. rtc ch11. uart ch12. irda ch13. iic ch14. iis ch15. spi ch16. ac97 ch17. usb host ch18. usb device ch19. modem ch20. gpio ch21. camera ch22. mpeg4-overview ch23. motion estimation ch24. motion compensation ch25. dctq ch26. vlx ch27. post ch28. lcd ch29. keypad ch30. adc & touch ch31. sd/mmc ch32. memory stick ch33. clock & power ch34. mechanical data
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-3 1 introduction (preliminary) 1.1 architectural overview the S3C24A0 is a 16/32-bit risc microprocessor, whic h is designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. to provide a sufficient h/w performance for the 2.5g & 3g communication services , the S3C24A0 adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. for the real time video conferenci ng, an optimized mpeg4 h/w encoder/dec oder is integrated. to reduce total system cost and enhance overall functiona lity, the S3C24A0 also includes following components: separate 16kb instruction and 16kb data cache, mmu to handle virt ual memory management, lcd controller (tft), camera interface, mpeg-4 me, mc, dctq, nand flash boot loader, system manager (power management & etc.), sdram controller, 2-ch uart, 4-ch dma, 4-ch timers, general i/o ports, iic-bus interface, usb host, sd host & multi-media card interface, memory stick interfac e, pll for clock generation & etc. the S3C24A0 can be used as a most powerful application processor for mobile s phones. for this application, the S3C24A0 has a modem interface to communicate with various modem chips. the S3C24A0 is developed using an arm926ej-s cor e, advanced 0.13um cmos standard cells and memory compliers. its low-power, simple, elegant and fully static -design scheme is particularly suitable for cost-sensitive and power-sensitive applications. also, the S3C24A0 adopt s a de-facto standard bus architecture ? the amba (advanced microcontroller bus architecture). one of outstanding features of the S3C24A0 is its cpu core, a 16/32 -bit arm926ej-s risc processor designed by arm, ltd. the arm926ej-s is a single chip m cu and java enabled microprocessor. the arm926ej-s also implements the mmu, the amba bus, and the harvard cac he architecture with separ ate 16kb instruction and 16kb data caches, each cache with an 8-word line length. by providing a complete set of common system peripheral s, the S3C24A0 minimizes overall system costs and eliminates the need to c onfigure additional components. 1.2 features this section summarizes the features of the S3C24A0. fi gure 1-1 is an overall block diagram of the S3C24A0. 1.2.1 microprocessor and overall architecture ? soc (system-on-chip) for mobile phones and general embedded applications. ? 16/32-bit risc architecture and powerful in struction set with arm926ej-s cpu core. ? arm?s jazelle java technology ? enhanced arm architecture mmu to support wince, symbian and linux ? instruction cache, data cache, wr ite buffer and physical address tag ram to reduce the effect of main memory bandwidth and latency on performance
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-4 ? 4 way set-associative cache with i-cache (16kb) and d-cache (16kb). ? 8-words per line with one valid bit and two dirty bits per line ? pseudo random or round robin replacement algorithm. ? write through or write back cache oper ation to update the main memory. ? the write buffer can hold 16 wo rds of data and four addresses. ? arm926ej-s core supports the arm debug architecture ? internal amba (advanced microcontroller bus architecture) (amba2.0, ahb/apb) ? dual ahb bus for high-performance processing (ahb-i & ahb-s) 1.2.2 memory subsystem ? high bandwidth memory subsystem with two access channels (accesses from two ahb buses) and three- channel memory ports ? double the bandwidth with the simultaneous access capability ? rom/sram/nor-flash/nand-flash channel ? one sdram channels ? up to 1gb address space ? low-power sdram interface support : mobile sdram function - ds : driver strength control - tcsr : temperature compens ated self-refresh control - pasr : partial array self-refresh control ? nand flash boot loader with the ecc circui try to support booting from nand flash - 4kb stepping stone - support 1g, 2g bit nand flash 1.2.3 general peripherals ? interrupt controller - 61 interrupt sources (1 watch dog timer, 5 timer, 6 uart, 18 external in terrupts, 4 dma, 2 rtc, 3 adc, 1 i2c, 1 ac97, 1 nand flash, 1 irda, 1 memory stick, 2 spi, 1 sdi, 2 usb (host and device), 1 keypad, 1 modem interface, 2 camera interface, 4 mpeg, 2 lcd, 1 battery fault, 1 post) - level/edge mode on external interrupt source. - programmable polarity of edge and level. - supports fiq (fast interrupt request) for very urgent interrupt request. ? timer with pwm (pulse width modulation) - 4-ch 16-bit timer with pwm / 1-ch 16-bit internal timer with dma-based or interrupt-based operation - programmable duty cycle, frequency, and polarity - dead-zone generation. - support external clock source.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-5 ? 16-bit watchdog timer. - interrupt request or system reset at time-out. ? 4-ch dma controller. - support memory to memory, io to me mory, memory to io, and io to io - burst transfer mode to enhance the transfer rate. ? rtc (real time clock) - full clock feature: msec, sec, mi n, hour, day, date, week, month, year. - 32.768 khz operation - alarm interrupt - time-tick interrupt 1.2.4 serial communication ? uart - 2-channel uart with dma-based or interrupt-based operation - supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive - supports external clock for the uart operation (xuclk) - programmable baud rate - supports irda 1.0 - loop back mode for testing - each channel has internal 64-byte tx fifo and 64-byte rx fifo ? irda - support irda 1.1 (1.152mbps and 4mbps) - support fifo operation in the mir and fir mode - configurable fifo size (16-byte or 64-byte) - support back-to-back transactions - support software selection temic-ibm or hp transceiver - support little-endian access ? iic-bus interface - 1-ch multi-master iic-bus - serial, 8-bit oriented and bi-directional data transfe rs can be made at up to 100 kbit/s in the standard mode ? iis-bus interface - 1-ch iis-bus for the audio-codec i nterface with dma-based operation - serial, 8/16-bit per channel data transfers - 128 bytes (64-byte + 64-byte) fifo for receive/transmit - supports iis format and msb-justified data format
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-6 ? spi interface - 2-ch serial peripheral interface protocol version 2.11 compatible - 2x8 bits shift regist er for receive/transmit. - dma-based or interrupt-based operation. ? ac97 audio-codec interface - 48khz 16-bit sampling - 1-ch stereo pcm inputs / 1-ch st ereo pcm outputs / 1-ch mic input ? usb host - 2-port usb host - complies with ohci rev. 1.0 - compatible with the usb s pecification version 1.1 ? usb device - 1-port usb device - 5 end-points for usb device - compatible with the usb s pecification version 1.1 1.2.5 parallel communication ? modem chip interface - 8-bit asynchronous sram interface-style interface - on-chip 2kb dual-ported sram buffer - interrupt request for data exchange - programmable interrupt port address ? 32-bit gpio - fully configurable 32-bit gpio 1.2.6 image and video processing ? camera inteface - itu601/itu656 ycbcr 4:2:2 8/16-bit mode - image down scaling capability for variable applications - digital zoom-in - image x, y-flip, 180 rotation - input image window cut - two master for dedicated dma operation - programmable burst length for dma operation - programmable polarity of video sync signals - wide horizontal line buffer (maximum 2048 pixel)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-7 - up to 4m pixel resolution support for scaled im age (image preview or motion video capturing) and 16m pixel for unscaled image (jpeg) - format conversion from ycrcb 4:2:2 to 4: 2:0 for codec, and to rgb 4:4:4 for preview ? hardware accelerated mpeg4 video encoding/decoding - a ahb interface - realtime mpeg-4 video encoding & decoding - up to simple profile at level 3 (352x288 at 30fps) - supports h.263 base line ? mpeg-4 me (motion estimation) - highly optimized hard-wired engine - unrestricted mode and adv anced prediction mode (4mv) - use the advanced mrmcs algorithm - half-pel search - programmable image size up to 2048x2048 - padding for macro-block basis - search range : [-16, 15.5] - intra/inter mode decision mc (motion compensation) ? mc (motion compensation) - highly optimized hard-wired engine - unrestricted mode and adv anced prediction mode (4mv) - half-pel search - programmable image size up to 2048x2048 - dedicated dma - macroblock-based pading - search range : [-64, 63.5] ? dctq - dct/idct/q/iq operations ? amba ahb interface - support mpeg-4 simple profile level 3 / h.263 base-line ? support programmable image size up to 4096x4096 - macroblock-based processing - rate control by qp information - local dma - support mpeg-4 encoding / decoding - support jpeg dct / idct operation - operation unit : 1mb(macroblock) ~ 1 frame
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-8 ? vlx - vlc/vld operations - amba ahb interface - support mpeg4 simple profile level 3/ h.263. baseline - macro block-based processing - dedicated dma - only dctq coefficient vlc/vld operation - only dc prediction operation in vlc ? post processor - dedicate dma with offset address - 3 channel scaling pipelines for video/graphis signal - input format : ycbcr4:2:0 , ycbcr4:2:2, or rgb 16b/24b - output format : rgb 16b/24b - programmable image size (source up to 4096x4096, destination up to 2048x2048) - programmable scale ratio (up-scale: up to max. destination size, down-scale: ~>1/64 in x & y) - format conversion for video signal (ycbcr4:2:0 or ycbcr4:2:2) - color space conversion (ycbcr2rgb) - separate processing clock from ahb interface clock 1.2.7 display control ? tft lcd interface - 18-bit parallel or 6bit*3 interface - 1/2/4/8-bpp palletized or 8/16/18-bpp non-palletized color-tff support - supports 640x480, 320x 240, 176x192 and others - up to 16 mbyte virtual screen size - supports multiple virtual display screen (suppor ts hardware horizontal/vertical scrolling) - programmable timing control for different display panels - dual buffer ? osd (on screen display) - realtime overlay plane multiplexing - programmable osd window positioning - per-pixel alpha blending for 18-bpp osd images - fixed alpha-value for 8-/16-/18-bpp osd image - 256-level alpha blending - 24-bit color key support - dual buffer
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-9 1.2.8 input devices ? keypad interface - provides internal debouncing filter - 5-input, 5-output pins for key scan in/out ? a/d converter and touch screen interface - 8-ch multiplexed adc - max. 500k samples/sec and 10-bit resolution 1.2.9 storage devices ? sd host - compatible with sd memory card protocol version 1.0 - compatible with sdio card protocol version 1.0 - 64 bytes fifo for tx/rx - dma based or interrupt based operation - compatible with multimedia ca rd protocol version 2.11 ? memory stick host - memory stick version 1.3 compliant 1.2.10 system management ? little endian format support ? system operating clock generation - two on-chip plls, mpll & upll - mpll generates the system refe rence clock, 200mhz@1.2v - upll generates clocks for the usb host/device, irda and camera ? power management - clock-off control for individual components - various power-down modes are available such as idle, stop and sleep - wake-up by one of external interrupts or by the rtc alarm interrupt, etc. 1.2.11 electrical characteristics ? operating conditions - - supply voltage for logic core: 1.25v +/- 0.05v - - external memory interface: 1.8v / 2.5v / 3.3v - - external i/o interface: 3.3v ? operational frequency - - max. 200mhz@1.25v
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-10 1.2.12 package ? 337-pin fbga (0.5mm pitch, 13mm x 13mm)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-11 mpeg4 h/w accelerator ahb-i ahb-s ahb to ahb bridge memory controller sdram memory controller sram/nor/nand /rom ahb to apb bridge a p b camera interface dctq/vlx me/mc digital display controller tft lcd interface modem interface usb 1.1 host 4-channel dma nand boot loader system/power down controller audio codec if timer*5 10-bit adc/ touch screen watch dog timer irda1.1 inst. data arm926ej usb1.1 device keypad intc postprocessor sd host memory stick host uart*2 gpio*32 i2c/i2s/s pi figure 1- 1 an overall block diagram of the S3C24A0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-12 1.3.2 pin assignment 337-pin fbga pin assignment #a1 index mark
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-13 table 1-1. 337-pin fbga pin assignments ? pin number order pin number pin name pin number pin name pin number pin name a01 xciydata[4] b11 xrdata[1] c21 xraddr [21] a02 vss_b b12 xrdata[3] c22 xfnfps a03 xcicdata[0] b13 xrdata[7] c23 xfnfadv a04 xciydata[7] b14 xraddr[5] d01 xjtdo a05 xcipclk b15 xrnwbe[0] d02 xjtdi a06 xvvd[5] b16 xrwen d03 xvvd[2] a07 xvvd[7] b17 xrcsn[2] d04 xcirstn a08 xvvclk b18 xrdata[14] d05 xciydata[5] a09 xvden b19 xraddr[11] d06 xcivsync a10 xcicdata[7] b20 xraddr[15] d07 xvvd[13] a11 xrdata[0] b21 xraddr[22] d08 xvvd[14] a12 xrdata[5] b22 xfale d09 xcicdata[5] a13 xraddr [3] b23 xfnfacyc d10 xjrtck a14 xraddr [7] c01 xjtms d11 xvvsync a15 xrnwbe[1] c02 xjtrstn d12 xvvd[19] a16 xrdata[8] c03 xciclk d13 xvvd[22] a17 xrdata[13] c04 xcicdata[1] d14 xraddr [4] a18 xraddr [10] c05 xvvd[4] d15 xraddr [2] a19 xraddr [16] c06 xcihref d16 xraddr [0] a20 xraddr [17] c07 xcicdata[4] d17 xraddr [14] a21 xraddr[20] c08 xcicdata[6] d18 xraddr [19] a22 xraddr [23] c09 xvhsync d19 xfcle a23 xfrnb[0] c10 xvvd[20] d20 xraddr [8] b01 xjtck c11 xvvd[23] d21 xraddr [12] b02 xciydata[0] c12 vdd_c d22 xfnfbw b03 xciydata[2] c13 xrdata[6] d23 xraddr [25] b04 xciydata[6] c14 xraddr[1] e01 xgpio[31] b05 xcicdata[2] c15 xraddr [6] e02 x2csda b06 xcicdata[3] c16 xrwaitn e03 x2cscl b07 xvvd[11] c17 xrcsn[1] e04 xciydata[1] b08 xvvd[15] c18 xrdata[10] e20 xfrnb[1] b09 xvvd[18] c19 xrdata[12] e21 xraddr [24] b10 xvvd[21] c20 xraddr [9] e22 xpdata[2]
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-14 table 1-1. 337-pin fbga pin assignments ? pin number order pin number pin name pin number pin name pin number pin name e23 xpdata[1] j21 vdd_a m09 vss_b f01 xgpio[28] j22 xpdqm[3] m10 vdd_f f02 xgpio[29] j23 xpdata[8] m11 vss f03 xgpio[30] k01 xgpio[11] m12 vss f04 xciydata[3] k02 xgpio[14] m13 vss f20 xraddr [18] k03 xgpio[16] m14 vdd_a f21 xpdata[0] k04 xvvd[12] m15 vss_d f22 xpdata[6] k11 vdd_b m20 xpaddr[2] f23 xpdata[3] k12 vss m21 xpdata[15] g01 xgpio[24] k13 vss_e m22 xpaddr[1] g02 xgpio[26] k20 xrdata[11] m23 xpaddr[3] g03 xgpio[27] k21 xpdata[9] n01 x97sync g04 xvvd[3] k22 xpdata[10] n02 x97resetn g20 xraddr [13] k23 xpdata[11] n03 xgpio[4] g21 xpdata[5] l01 xgpio[7] n04 xgpio[8] g22 xpdqm[0] l02 xgpio[10] n09 vdd_a g23 xpdata[7] l03 xgpio[12] n10 vdd_b h01 xgpio[20] l04 xgpio[21] n11 vss h02 xgpio[23] l09 vdd_c n12 vss h03 xgpio[22] l10 vdd_c n13 vss h04 xvvd[6] l11 vss n14 vss_d h20 xpdata[4] l12 vss n15 vdd_d h21 vdd_d l13 vss n20 xrdata[9] h22 xpdqm[1] l14 vdd_e n21 xpaddr[4] h23 xpdqm[2] l15 vss_d n22 xpaddr[5] j01 xgpio[17] l20 xpdata[14] n23 xpaddr[6] j02 xgpio[18] l21 xpdata[12] p01 xurtsn j03 xgpio[25] l22 xpdata[13] p02 x97sdo j04 xvvd[10] l23 xpaddr[0] p03 x97bitclk j11 vss_b m01 xgpio[0] p04 xgpio[5] j12 vss_e m02 xgpio[6] p11 vss_b j13 vdd_e m03 vdd_b p12 vdd_f j20 xrdata[15] m04 xgpio[19] p13 vss_d
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-15 table 1-1. 337-pin fbga pin assignments ? pin number order pin number pin name pin number pin name pin number pin name p20 xrcsn[0] v03 xgtmode[3] y20 vdd_d p21 xpdata[16] v04 xuclk y21 xpdata[25] p22 xpaddr[7] v20 xrdata[2] y22 xpdata[27] p23 xpdata[18] v21 xpdata[29] y23 xpdata[26] r01 xgtmode[2] v22 xpwen aa01 xrtcxti r02 xurxd v23 xpcasn aa02 xgrefclksel[0] r03 xgpio[2] w01 xgtmode[1] aa03 xgpwroffn r04 xgpio[15] w02 xspimiso aa04 xadcain[5] r11 vdd_a w03 xspissin[0] aa05 xadcavref r12 vdd_b w04 x2sclk aa06 xadcain[2] r13 vss_d w20 vdd_d aa07 gnd10 r20 xroen w21 vdd_a aa08 vdd13 r21 xpdata[17] w22 xpcsn[0] aa09 xsresetn r22 xpdata[19] w23 xpcsn[1] aa10 xsxtout r23 xpsclk y01 xswresetn aa11 xusdp[0] t01 x2scdclk y02 xgtmode[0] aa12 xusdn[0] t02 xuctsn y03 xspiclk aa13 xmsbs t03 x97sdi y04 x2sdi aa14 xmiwen t04 xgpio[13] y05 xgbatfltn aa15 xmiadr[8] t20 xpdata[24] y06 xgpio[1] aa16 xmiadr[6] t21 xpdata[20] y07 xgpio[3] aa17 xmidata[6] t22 xpdata[21] y08 vdd15 aa18 vdd_a t23 xpdata[23] y09 xsrstoutn aa19 xmidata[2] u01 x2sdo y10 xuddp aa20 xmiadr[0] u02 x2slrck y11 xsddat[3] aa21 vdd_d u03 xutxd y12 vdd20(vddpadusb) aa22 xpdata[31] u04 xgpio[9] y13 xmssdio aa23 xpdata[28] u20 xrdata[4] y14 xmspi ab01 vdd10 u21 xpdata[22] y15 xmicsn ab02 xadcain[7] u22 xpcke y16 xmiadr[10] ab03 xrtcxto u23 xprasn y17 xpaddr[13] ab04 xgrefclksel[1] v01 xspimosi y18 xmiadr[4] ab05 xadcain[0] v02 xspissin[1] y19 xmiadr[2] ab06 vdd11
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-16 table 1-1. 337-pin fbga pin assignments ? pin number order pin number pin name pin number pin name pin number pin name ab07 gnd12 ab21 xpaddr[11] ac12 xsddat[2] ab08 xsupllcap ab22 xpdata[30] ac13 xsddat[0] ab09 xsextclk ab23 xpaddr[8] ac14 xmiadr[9] ab10 xusdp[1] ac01 gnd9(vssrtc) ac15 xmiadr[5] ab11 xuddn ac02 xadcain[6] ac16 xmidata[5] ab12 xsddat[1] ac03 xadcain[4] ac17 xmidata[3] ab13 gnd19(vsspadusb) ac04 xadcain[3] ac18 xmidata[1] ab14 xmioen ac05 xadcain[1] ac19 xmiadr[3] ab15 xmiadr[7] ac06 xsmpllcap ac20 xpaddr[14] ab16 xmidata[7] ac07 gnd14 ac21 xpaddr[12] ab17 xmidata[4] ac08 xgmonhclk ac22 xpaddr[10] ab18 xmiirqn ac09 xsxtin ac23 xpaddr[9] ab19 xmidata[0] ac10 xusdn[1] ab20 xmiadr[1] ac11 xmssclko
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-17 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) aa7 vssadc vssadc p p pp p ab7 vssmpll vssmpll p p pp p ac7 vssupll vssupll p p pp p ab13 vsspadusb vsspadusb p p pp p ac1 vssrtc vssrtc p p pp p aa18 vddlogic vddlogic p p pp p j21 vddlogic vddlogic p p pp p m14 vddlogic vddlogic p p pp p n9 vddlogic vddlogic p p pp p r11 vddlogic vddlogic p p pp p w21 vddlogic vddlogic p p pp p k11 vddpadio vddpadio p p pp p m3 vddpadio vddpadio p p pp p n10 vddpadio vddpadio p p pp p r12 vddpadio vddpadio p p pp p c12 vddarm vddarm p p pp p l10 vddarm vddarm p p pp p l9 vddarm vddarm p p pp p aa21 vddpadsdram vddpadsdram p p pp p h21 vddpadsdram vddpadsdram p p pp p n14 vss vss p p pp p n15 vddpadsdram vddpadsdram p p pp p w20 vddpadsdram vddpadsdram p p pp p y20 vddpadsdram vddpadsdram p p pp p j13 vddpadflash vddpadflash p p pp p l14 vddpadflash vddpadflash p p pp p m10 vddalive vddalive p p pp p p12 vddalive vddalive p p pp p ab1 vddrtc vddrtc p p pp p ab6 vddadc vddadc p p pp p aa8 vddmpll vddmpll p p pp p y8 vddupll vddupll p p pp p y12 vddpadusb vddpadusb p p pp p k12 vss vss p p pp p l11 vss vss p p pp p l12 vss vss p p pp p l13 vss vss p p pp p
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-18 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) m11 vss vss p p pp p m12 vss vss p p pp p m13 vss vss p p pp p n11 vss vss p p pp p n12 vss vss p p pp p n13 vss vss p p pp p a2 vsspadio vsspadio p p pp p j11 vsspadio vsspadio p p pp p m9 vsspadio vsspadio p p pp p p11 vsspadio vsspadio p p pp p l15 vsspadsdram vsspadsdram p p pp p m15 vsspadsdram vsspadsdram p p pp p p13 vsspadsdram vsspadsdram p p pp p r13 vsspadsdram vsspadsdram p p pp p j12 vsspadflash vsspadflash p p pp p k13 vsspadflash vsspadflash p p pp p e3 x2cscl x2cscl i/o i/h l or i h phbsud8sm e2 x2csda x2csda i/o i/h l or i h phbsud8sm t1 x2scdclk x2scdclk o h or l/l hi-z or h or l h phot8 w4 x2sclk x2sclk i/o l/l/l h or l or i l phbsu100ct8sm y4 x2sdi x2sdi i i - - phisu u1 x2sdo x2sdo o l/l hi-z or h or l l phot8 u2 x2slrck x2slrck i/o h/l/l h or l or i pre phbsu100ct8sm p3 x97bitclk x97bitclk i i - - phis n2 x97resetn x97resetn o l/l hi-z or h or l h phot8 t3 x97sdi x97sdi i i - - phisu p2 x97sdo x97sdo o l/l hi-z or h or l l phot8 n1 x97sync x97sync o l/l hi-z or h or l l phot8 ab5 xadcain[0] xadcain[0] ain i - - phiar10_abb ac5 xadcain[1] xadcain[1] ain i - - phiar10_abb aa6 xadcain[2] xadcain[2] ain i - - phiar10_abb
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-19 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) ac4 xadcain[3] xadcain[3] ain i - - phiar10_abb ac3 xadcain[4] xadcain[4] ain i - - phiar10_abb aa4 xadcain[5] xadcain[5] ain i - - phiar10_abb ac2 xadcain[6] xadcain[6] ain i - - phiar10_abb ab2 xadcain[7] xadcain[7] ain i - - phiar10_abb aa5 xadcavref xadcavref ain i - - phia_abb a3 xcicdata[0] xcicdata[0] i i/h/l - - phbsu100ct8sm c4 xcicdata[1] xcicdata[1] i i/h/l - - phbsu100ct8sm b5 xcicdata[2] xcicdata[2] i i/h/l - - phbsu100ct8sm b6 xcicdata[3] xcicdata[3] i i/h/l - - phbsu100ct8sm c7 xcicdata[4] xcicdata[4] i i/h/l - - phbsu100ct8sm d9 xcicdata[5] xcicdata[5] i i/h/l - - phbsu100ct8sm c8 xcicdata[6] xcicdata[6] i i/h/l - - phbsu100ct8sm a10 xcicdata[7] xcicdata[7] i i/h/l - - phbsu100ct8sm c3 xciclk xciclk o l/l hi-z or h or l l phot12sm c6 xcihref xcihref i i - - phis a5 xcipclk xcipclk i i - - phis d4 xcirstn xcirstn o l/l hi-z or h or l pre phot8 d6 xcivsync xcivsync i i - - phis b2 xciydata[0] xciydata[0] i i - - phis e4 xciydata[1] xciydata[1] i i - - phis b3 xciydata[2] xciydata[2] i i - - phis f4 xciydata[3] xciydata[3] i i - - phis a1 xciydata[4] xciydata[4] i i - - phis d5 xciydata[5] xciydata[5] i i - - phis b4 xciydata[6] xciydata[6] i i - - phis a4 xciydata[7] xciydata[7] i i - - phis b22 xfale xfale o l/l hi-z or h or l l phot8 d19 xfcle xfcle o l/l hi-z or h or l l phot8
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-20 table 1-2. 337-pin fbga pin assignments pin numbe r name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullu p i/o state@sleep mode i/o state@stop mode cell type (24a0a) b23 xfnfacyc xfnfacyc i i - - phis c23 xfnfadv xfnfadv i i - - phis d22 xfnfbw xfnfbw i i - - phis c22 xfnfps xfnfps i i - - phis a23 xfrnb[0] xfrnb[0] i i - - phisu e20 xfrnb[1] xfrnb[1] i i - - phisu y5 xgbatflt xgbatflt i h - - phis ac8 xgmonhclk xgmonhclk o l/l hi-z or h or l l phot8 m1 xgpio[0]/eint0 xgpio[0] i/o i/h/l h or l or i - phbsu100ct8s m y6 xgpio[1]/eint1 xgpio[1] i/o i/h/l h or l or i - phbsu100ct8s m l2 xgpio[10]/ymon xgpio[10] i/o i/h/l h or l or i - phbsu100ct8s m k1 xgpio[11]/eint11 xgpio[11] i/o i/h/l h or l or i - phbsu100ct8s m l3 xgpio[12]/eint12/xmon xgpio[12] i/o i/h/l h or l or i - phbsu100ct8s m t4 xgpio[13]/eint13/xpon xgpio[13] i/o i/h/l h or l or i - phbsu100ct8s m k2 xgpio[14]/eint14/rtc_almint x gpio[14] i/o i/h/l h or l or i - phbsu100ct8s m r4 xgpio[15]/eint15/xspimosi xgpio[15] i/o i/h/l h or l or i - phbsu100ct8s m k3 xgpio[16]/eint16/xspimiso xgpio[16] i/o i/h/l h or l or i - phbsu100ct8s m j1 xgpio[17]/eint17/xspiclk xgpio[17] i/o i/h/l h or l or i - phbsu100ct8s m j2 xgpio[18]/eint18/xkprow0 xgp io[18] i/o i/h/l h or l or i - phbsu100ct8s m m4 xgpio[19]/pwm_eclk/xkprow 1 xgpio[19] i/o i/h/l h or l or i - phbsu100ct8s m r3 xgpio[2]/eint2/pwm_tout0 xgp io[2] i/o i/h/l h or l or i - phbsu100ct8s m h1 xgpio[20]/pwm_tout0/ xkprow2 xgpio[20] i/o i/h/l h or l or i - phbsu100ct8s m l4 xgpio[21]/pwm_tout1/ xkprow3 xgpio[21] i/o i/h/l h or l or i - phbsu100ct8s m
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-21 table 1-2. 337-pin fbga pin assignments pin numbe r name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullu p i/o state@sleep mode i/o state@stop mode cell type (24a0a) h3 xgpio[22]/pwm_tout2/xkprow4 xgpio[22] i/o i/h/l h or l or i - phbsu100ct8 s m h2 xgpio[23]/pwm_tout3/xkpcol0 xgpio[23] i/o i/h/l h or l or i - phbsu100ct8 s m g1 xgpio[24]/extdma_req0/ xkpcol1 xgpio[24] i/o i/h/l h or l or i - phbsu100ct8 s m j3 xgpio[25]/extdma_req1/ xkpcol2 xgpio[25] i/o i/h/l h or l or i - phbsu100ct8 s m g2 xgpio[26]/extdma_ack0/ xkpcol3 xgpio[26] i/o i/h/l h or l or i - phbsu100ct8 s m g3 xgpio[27]/extdma_ack1/xkpcol4 xgpio[27] i/o i/h/l h or l or i - phbsu100ct8 s m f1 xgpio[28]/xuctsn1/rtc_almint xgpio[28] i/o i/h/l h or l or i - phbsu100ct8 s m f2 xgpio[29]/xurtsn1/irda_sdbw xgpio[29] i/o i/h/l h or l or i - phbsu100ct8 s m y7 xgpio[3]/eint3/pwm_tout1 xgp io[3] i/o i/h/l h or l or i - phbsu100ct8 s m f3 xgpio[30]/xutxd1/ir da_txd xgpio[30] i/o i/h/l h or l or i - phbsu100ct8 s m e1 xgpio[31]/xurxd1/ irda_rxd xgpio[31] i/o i/h/l h or l or i - phbsu100ct8 s m n3 xgpio[4]/eint4/pwm_tout2 xgp io[4] i/o i/h/l h or l or i - phbsu100ct8 s m p4 xgpio[5]/eint5/ pwm_tout3 xgp io[5] i/o i/h/l h or l or i - phbsu100ct8 s m m2 xgpio[6]/eint6/extdma_req0 xgp io[6] i/o i/h/l h or l or i - phbsu100ct8 s m l1 xgpio[7]/eint7 extdma_req1 xgpio[7] i/o i/h/l h or l or i - phbsu100ct8 s m n4 xgpio[8]/eint8/ extdma_ack0 xgp io[8] i/o i/h/l h or l or i - phbsu100ct8 s m u4 xgpio[9]/eint9 extdma_ack1 xgp io[9] i/o i/h/l h or l or i - phbsu100ct8 s m aa3 xgpwroffn xgpwroffn o h l h phob8 aa2 xgrefclksel[0] xgrefclksel[0] i h - - phis ab4 xgrefclksel[1] xgrefclksel[1] i h - - phis
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-22 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) y2 xgtmode[0] xgtmode[0] i i - - phis w1 xgtmode[1] xgtmode[1] i i - - phis r1 xgtmode[2] xgtmode[2] i i - - phis v3 xgtmode[3] xgtmode[3] i i - - phis d10 xjrtck xjrtck o l - - phob8 b1 xjtck xjtck i i - - phis d2 xjtdi xjtdi i i - - phisu d1 xjtdo xjtdo o i/h hi-z or h or l hi-z phot8 c1 xjtms xjtms i i - - phisu c2 xjtrstn xjtrstn i i - - phisu aa20 xmiadr[0] xmiadr[0] i i/h/l - - phbsu100ct8sm ab20 xmiadr[1] xmiadr[1] i i/h/l - - phbsu100ct8sm y16 xmiadr[10] xmiadr[10] i i/h/l - - phbsu100ct8sm y19 xmiadr[2] xmiadr[2] i i/h/l - - phbsu100ct8sm ac19 xmiadr[3] xmiadr[3] i i/h/l - - phbsu100ct8sm y18 xmiadr[4] xmiadr[4] i i/h/l - - phbsu100ct8sm ac15 xmiadr[5] xmiadr[5] i i/h/l - - phbsu100ct8sm aa16 xmiadr[6] xmiadr[6] i i/h/l - - phbsu100ct8sm ab15 xmiadr[7] xmiadr[7] i i/h/l - - phbsu100ct8sm aa15 xmiadr[8] xmiadr[8] i i/h/l - - phbsu100ct8sm ac14 xmiadr[9] xmiadr[9] i i/h/l - - phbsu100ct8sm y15 xmicsn xmicsn i i - - phisu ab19 xmidata[0] xmidata[0] i/o i/h/l h or l or i - phbsu100ct8sm ac18 xmidata[1] xmidata[1] i/o i/h/l h or l or i - phbsu100ct8sm aa19 xmidata[2] xmidata[2] i/o i/h/l h or l or i - phbsu100ct8sm ac17 xmidata[3] xmidata[3] i/o i/h/l h or l or i - phbsu100ct8sm ab17 xmidata[4] xmidata[4] i/o i/h/l h or l or i - phbsu100ct8sm ac16 xmidata[5] xmidata[5] i/o i/h/l h or l or i - phbsu100ct8sm aa17 xmidata[6] xmidata[6] i/o i/h/l h or l or i - phbsu100ct8sm ab16 xmidata[7] xmidata[7] i/o i/h/l h or l or i - phbsu100ct8sm
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-23 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) ab18 xmiirqn xmiirqn o h/l hi-z or h or l h phot8 ab14 xmioen xmioen i i - - phisu aa14 xmiwen xmiwen i i - - phisu aa13 xmsbs xmsbs o l/l hi-z or h or l l phot8 y14 xmspi xmspi i i - - phis ac11 xmssclko xmssclko o h/l hi-z or h or l h phot8 y13 xmssdio xmssdio i/o i/h/l h or l or i - phbsu100ct12s m l23 xpaddr[0] xpaddr[0] o l/l hi-z or h or l pre phot12sm m22 xpaddr[1] xpaddr[1] o l/l hi-z or h or l pre phot12sm ac22 xpaddr[10] xpaddr[10] o l/l hi-z or h or l pre phot12sm ab21 xpaddr[11] xpaddr[11] o l/l hi-z or h or l pre phot12sm ac21 xpaddr[12] xpaddr[12] o l/l hi-z or h or l pre phot12sm y17 xpaddr[13] xpaddr[13] o l/l hi-z or h or l pre phot12sm ac20 xpaddr[14] xpaddr[14] o l/l hi-z or h or l pre phot12sm m20 xpaddr[2] xpaddr[2] o l/l hi-z or h or l pre phot12sm m23 xpaddr[3] xpaddr[3] o l/l hi-z or h or l pre phot12sm n21 xpaddr[4] xpaddr[4] o l/l hi-z or h or l pre phot12sm n22 xpaddr[5] xpaddr[5] o l/l hi-z or h or l pre phot12sm n23 xpaddr[6] xpaddr[6] o l/l hi-z or h or l pre phot12sm p22 xpaddr[7] xpaddr[7] o l/l hi-z or h or l pre phot12sm ab23 xpaddr[8] xpaddr[8] o l/l hi-z or h or l pre phot12sm ac23 xpaddr[9] xpaddr[9] o l/l hi-z or h or l pre phot12sm v23 xpcasn xpcasn o h/l hi-z or h or l pre phot12sm u22 xpcke xpcke o l/l hi-z or h or l l phot12sm
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-24 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) w22 xpcsn[0] xpcsn[0] o h/l hi-z or h or l h phot12sm w23 xpcsn[1] xpcsn[1] o h/l hi-z or h or l h phot12sm f21 xpdata[0] xpdata[0] i/o i/h/l h or l or i - phbsu100ct12s m e23 xpdata[1] xpdata[1] i/o i/h/l h or l or i - phbsu100ct12s m k22 xpdata[10] xpdata[10] i/o i/h/l h or l or i - phbsu100ct12s m k23 xpdata[11] xpdata[11] i/o i/h/l h or l or i - phbsu100ct12s m l21 xpdata[12] xpdata[12] i/o i/h/l h or l or i - phbsu100ct12s m l22 xpdata[13] xpdata[13] i/o i/h/l h or l or i - phbsu100ct12s m l20 xpdata[14] xpdata[14] i/o i/h/l h or l or i - phbsu100ct12s m m21 xpdata[15] xpdata[15] i/o i/h/l h or l or i - phbsu100ct12s m p21 xpdata[16] xpdata[16] i/o i/h/l h or l or i - phbsu100ct12s m r21 xpdata[17] xpdata[17] i/o i/h/l h or l or i - phbsu100ct12s m p23 xpdata[18] xpdata[18] i/o i/h/l h or l or i - phbsu100ct12s m r22 xpdata[19] xpdata[19] i/o i/h/l h or l or i - phbsu100ct12s m e22 xpdata[2] xpdata[2] i/o i/h/l h or l or i - phbsu100ct12s m t21 xpdata[20] xpdata[20] i/o i/h/l h or l or i - phbsu100ct12s m t22 xpdata[21] xpdata[21] i/o i/h/l h or l or i - phbsu100ct12s m u21 xpdata[22] xpdata[22] i/o i/h/l h or l or i - phbsu100ct12s m t23 xpdata[23] xpdata[23] i/o i/h/l h or l or i - phbsu100ct12s m t20 xpdata[24] xpdata[24] i/o i/h/l h or l or i - phbsu100ct12s m y21 xpdata[25] xpdata[25] i/o i/h/l h or l or i - phbsu100ct12s m y23 xpdata[26] xpdata[26] i/o i/h/l h or l or i - phbsu100ct12s m y22 xpdata[27] xpdata[27] i/o i/h/l h or l or i - phbsu100ct12s m
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-25 table 1-2. 337-pin fbga pin assignments pin numbe r name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) aa23 xpdata[28] xpdata[28] i/o i/h/l h or l or i - phbsu100ct12s m v21 xpdata[29] xpdata[29] i/o i/h/l h or l or i - phbsu100ct12s m f23 xpdata[3] xpdata[3] i/o i/h/l h or l or i - phbsu100ct12s m ab22 xpdata[30] xpdata[30] i/o i/h/l h or l or i - phbsu100ct12s m aa22 xpdata[31] xpdata[31] i/o i/h/l h or l or i - phbsu100ct12s m h20 xpdata[4] xpdata[4] i/o i/h/l h or l or i - phbsu100ct12s m g21 xpdata[5] xpdata[5] i/o i/h/l h or l or i - phbsu100ct12s m f22 xpdata[6] xpdata[6] i/o i/h/l h or l or i - phbsu100ct12s m g23 xpdata[7] xpdata[7] i/o i/h/l h or l or i - phbsu100ct12s m j23 xpdata[8] xpdata[8] i/o i/h/l h or l or i - phbsu100ct12s m k21 xpdata[9] xpdata[9] i/o i/h/l h or l or i - phbsu100ct12s m g22 xpdqm[0] xpdqm[0] o h/l hi-z or h or l - phot12sm h22 xpdqm[1] xpdqm[1] o h/l hi-z or h or l - phot12sm h23 xpdqm[2] xpdqm[2] o h/l hi-z or h or l - phot12sm j22 xpdqm[3] xpdqm[3] o h/l hi-z or h or l - phot12sm u23 xprasn xprasn o h/l hi-z or h or l - phot12sm r23 xpsclk xpsclk i/o h or l /l h or l or i l phbst12 v22 xpwen xpwen o h/l hi-z or h or l h phot12sm d16 xraddr[0] xraddr[0] o l/l hi-z or h or l pre phot8 c14 xraddr[1] xraddr[1] o l/l hi-z or h or l pre phot8 a18 xraddr[10] xraddr[10] o l/l hi-z or h or l pre phot8 b19 xraddr[11] xraddr[11] o l/l hi-z or h or l pre phot8 d21 xraddr[12] xraddr[12] o l/l hi-z or h or l pre phot8
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-26 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) g20 xraddr[13] xraddr[13] o l/l hi-z or h or l pre phot8 d17 xraddr[14] xraddr[14] o l/l hi-z or h or l pre phot8 b20 xraddr[15] xraddr[15] o l/l hi-z or h or l pre phot8 a19 xraddr[16] xraddr[16] o l/l hi-z or h or l pre phot8 a20 xraddr[17] xraddr[17] o l/l hi-z or h or l pre phot8 d15 xraddr[2] xraddr[2] o l/l hi-z or h or l pre phot8 a13 xraddr[3] xraddr[3] o l/l hi-z or h or l pre phot8 d14 xraddr[4] xraddr[4] o l/l hi-z or h or l pre phot8 b14 xraddr[5] xraddr[5] o l/l hi-z or h or l pre phot8 c15 xraddr[6] xraddr[6] o l/l hi-z or h or l pre phot8 a14 xraddr[7] xraddr[7] o l/l hi-z or h or l pre phot8 d20 xraddr[8] xraddr[8] o l/l hi-z or h or l pre phot8 c20 xraddr [9] xraddr [9] o l/l hi-z or h or l pre phot8 f20 xraddr[18] xraddr[18] o l/l/h hi-z or h or l pre phbsu100ct8sm d18 xraddr[19] xraddr[19] o l/l/h hi-z or h or l pre phbsu100ct8sm a21 xraddr[20] xraddr[20] o l/l/h hi-z or h or l pre phbsu100ct8sm c21 xraddr[21] xraddr[21] o l/l/h hi-z or h or l pre phbsu100ct8sm b21 xraddr[22] xraddr[22] o l/l/h hi-z or h or l pre phbsu100ct8sm a22 xraddr[23] xraddr[23] o l/l/h hi-z or h or l pre phbsu100ct8sm e21 xraddr[24] xraddr[24] o l/l/h hi-z or h or l pre phbsu100ct8sm d23 xraddr[25] xraddr[25] o l/l/h hi-z or h or l pre phbsu100ct8sm p20 xrcsn[0] xrcsn[0] o h/l hi-z or h or l pre phot8
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-27 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) c17 xrcsn[1] xrcsn[1] o h/l hi-z or h or l pre phot8 b17 xrcsn[2] xrcsn[2] o h/l hi-z or h or l pre phot8 a11 xrdata[0] xrdata[0] i/o i/h/l h or l or i - phbsu100ct8sm b11 xrdata[1] xrdata[1] i/o i/h/l h or l or i - phbsu100ct8sm c18 xrdata[10] xrdata[10] i/o i/h/l h or l or i - phbsu100ct8sm k20 xrdata[11] xrdata[11] i/o i/h/l h or l or i - phbsu100ct8sm c19 xrdata[12] xrdata[12] i/o i/h/l h or l or i - phbsu100ct8sm a17 xrdata[13] xrdata[13] i/o i/h/l h or l or i - phbsu100ct8sm b18 xrdata[14] xrdata[14] i/o i/h/l h or l or i - phbsu100ct8sm j20 xrdata[15] xrdata[15] i/o i/h/l h or l or i - phbsu100ct8sm v20 xrdata[2] xrdata[2] i/o i/h/l h or l or i - phbsu100ct8sm b12 xrdata[3] xrdata[3] i/o i/h/l h or l or i - phbsu100ct8sm u20 xrdata[4] xrdata[4] i/o i/h/l h or l or i - phbsu100ct8sm a12 xrdata[5] xrdata[5] i/o i/h/l h or l or i - phbsu100ct8sm c13 xrdata[6] xrdata[6] i/o i/h/l h or l or i - phbsu100ct8sm b13 xrdata[7] xrdata[7] i/o i/h/l h or l or i - phbsu100ct8sm a16 xrdata[8] xrdata[8] i/o i/h/l h or l or i - phbsu100ct8sm n20 xrdata[9] xrdata[9] i/o i/h/l h or l or i - phbsu100ct8sm b15 xrnwbe[0] xrnwbe[0] o h/l hi-z or h or l pre phot8 a15 xrnwbe[1] xrnwbe[1] o h/l hi-z or h or l pre phot8 r20 xroen xroen o h/l hi-z or h or l h phot8
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-28 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) aa1 xrtcxti xrtcxti ain l --rtc_osc ab3 xrtcxto xrtcxto aout x - - rtc_osc c16 xrwaitn xrwaitn i i - - phis b16 xrwen xrwen o h/l hi-z or h or l h phot8 ac13 xsddat[0] xsddat[0] i/o i/h/l h or l or i - phbsu100ct12sm ab12 xsddat[1] xsddat[1] i/o i/h/l h or l or i - phbsu100ct12sm ac12 xsddat[2] xsddat[2] i/o i/h/l h or l or i - phbsu100ct12sm y11 xsddat[3] xsddat[3] i/o i/h/l h or l or i - phbsu100ct12sm ab9 xsextclk xsextclk i i - - phis ac6 xsmpllcap xsmpllcap aout x - - phob1_abb y3 xspiclk xspiclk i/o i/h/l h or l or i - phtbsu100ct8sm w2 xspimiso xspimiso i/o h/l/l h or l or i h phtbsu100ct8sm v1 xspimosi xspimosi i/o i/h/l h or l or i - phtbsu100ct8sm w3 xspissin[0] xspissin[0] i i - - phisu v2 xspissin[1] xspissin[1] i i - - phisu aa9 xsresetn xsresetn i l - - phisu y9 xsrstoutn xsrstoutn o l hi-z or h or l h phot8 ab8 xsupllcap xsupllcap aout x - - phob1_abb y1 xswresetn xswresetn i l - - phisu ac9 xsxtin xsxtin i h or l - - phsoscm26_schmit t aa10 xsxtout xsxtout o h or l - - phsoscm26_schmit t v4 xuclk xuclk i i - - phis t2 xuctsn xuctsn i i - - phis ab11 xuddn xuddn i/o i h or l or i - pbusb1 y10 xuddp xuddp i/o i h or l or i - pbusb1 p1 xurtsn xurtsn o h/l hi-z or h or l h phot8 r2 xurxd xurxd i i - - phisu aa12 xusdn[0] xusdn[0] i/o x h or l or i - pbusb1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-29 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) ac10 xusdn[1] xusdn[1] i/o x h or l or i - pbusb1 aa11 xusdp[0] xusdp[0] i/o x h or l or i - pbusb1 ab10 xusdp[1] xusdp[1] i/o x h or l or i - pbusb1 u3 xutxd xutxd o h/l hi-z or h or l h phot8 a9 xvden xvden o l/l hi-z or h or l l phot8 c9 xvhsync xvhsync o l/l hi-z or h or l pre phot8 a8 xvvclk xvvclk o h or l /l hi-z or h or l l phot12sm j4 xvvd[6] xvvd[6] o l/l h or l or i pre phot12sm b7 xvvd[7] xvvd[7] o l/l h or l or i pre phot12sm k4 xvvd[8] xvvd[8] o l/l h or l or i pre phot12sm d7 xvvd[9] xvvd[9] o l/l h or l or i pre phot12sm d8 xvvd[10] xvvd[10] o l/l h or l or i pre phot12sm b8 xvvd[11] xvvd[11] o l/l h or l or i pre phot12sm b9 xvvd[12] xvvd[12] o l/l h or l or i pre phot12sm d12 xvvd[13] xvvd[13] o l/l h or l or i pre phot12sm d3 xvvd[0] xvvd[0] o l/l h or l or i pre phot12sm c10 xvvd[14] xvvd[14] o l/l h or l or i pre phot12sm b10 xvvd[15] xvvd[15] o l/l h or l or i pre phot12sm d13 xvvd[16] xvvd[16] o l/l h or l or i pre phot12sm c11 xvvd[17] xvvd[17] o l/l h or l or i pre phot12sm g4 xvvd[1] xvvd[1] o l/l h or l or i pre phot12sm
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-30 table 1-2. 337-pin fbga pin assignments pin number name default function i/o i/o state@ reset mode (data/en/pullupen) en(l)=>output pullupen(l)=>pullup i/o state@sleep mode i/o state@stop mode cell type (24a0a) c5 xvvd[2] xvvd[2] o l/l h or l or i pre phot12sm a6 xvvd[3] xvvd[3] o l/l h or l or i pre phot12sm h4 xvvd[4] xvvd[4] o l/l h or l or i pre phot12sm a7 xvvd[5] xvvd[5] o l/l h or l or i pre phot12sm d11 xvvsync xvvsync o l/l hi-z or h or l l phot8 notes: 1.?-? mark indicates the unchanged pin state 2. hi-z or pre means hi-z or previous value 3. p, i and o mean power, input and output respectively 4. ai/ao means analog input/output the table below shows i/o types and the descriptions. i/o type descriptions vdd12ih 1.2v vdd for alive vdd12ih_core 1.2v vdd for internal logic vdd33oph 3.3v vdd for external logic vdd33th_abb 3.3v vdd for analog circuit vdd30th_rtc 3.3v vdd for rtc circuit vdd33th_abb 3.3v vdd for pll circuit vss vss phis input pad, lvcmos schmitt-trigger level phisu input pad, schmitt-trigger level, pull-up phisd input pad, schmitt-trigger level, pull-down pbusb usb pad phot8 output pad, tri-state, io=8ma phob8 output pad, io=8ma phot12sm output pad, tri-state, medium slew rate, io=12ma
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-31 phbst12sm bi-directional pad, lvcmos schmitt-trigger, pull-up resistor with control, tri-state, io=12ma pbusb1 usb pad rtc-osc rtc x-tal phob1-abb analog pad phiar10_abb analog input pad with 10-ohm resistor phia_abb analog input pad phsoscm26_shmitt oscillator cell with enable and feedback resistor phbsu100ct8sm bi-directional pad, lvcmos schmitt-trigger, 100kohm pull-up resistor with control, tri-state, io=8ma phbsu100ct12sm bi-directional pad, lvcmos schmitt-trigger, 100kohm pull-up resistor with control, tri-state, io=12ma phbsud8sm bi-directional pad, schmitt-tri gger, pull-up resistor with, open-drain control, io=8ma note) phbsu100ct8sm means a bi-directional pad, but this means input pad so long as phbsu100ct8sm is used for xcicdata[7:0]
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-32 1.3 pin descriptions 1.3.1 i/o signal descriptions 1.3.1.1 external memory interface ? shared memory bus (rom/sram/nor flash/nand flash/external bus) signal i/o description xraddr[25:0] o xraddr[25:0] (address bus for shar ed memory) outputs the memory address of the corresponding bank . xrdata[15:0] io xrdata[15:0] (data bus) input s data during memory r ead and outputs data during memory write. the bus width is programmable among 8/16-bit. xrcsn[2:0] o xrcsn[2:0] (chip select) are activa ted when the address of a memory is within the address region of each bank. the number of access cycles and the bank size can be programmed. xrwen o xrwen (write enable) indicates t hat the current bus cycle is a write cycle. xroen o xroen (output enable) indicates t hat the current bus cycle is a read cycle. xrwaitn i xrwaitn requests to prolong a current bus cycle. as long as xrwaitn n is l, the current bus cycle cannot be completed. xrnwbe[1:0] o write byte enable xfcle o nand flash command latch enable xfale o nand flash address latch enable xfnfps i nand flash page size (0:256hword, 1:512byte) or advanced page size(0:1k hword , 1:2k byte) xfnfbw i nand flash bus width (0:8-bit, 1:16-bit) xfnfacyc i nand flash address step (0:3-step, 1:4-step) or advanced address step(0:4-step, 1:5-step) xfnfadv i to support advanced 2g nand flash xfrnb[1:0] i nand flash ready and busy ? sdram bank 0 signal i/o description xpcsn[1:0] o sdram bank 0 chip select xpcasn o sdram bank 0 column address strobe xprasn o sdram bank 0 row address strobe xpwen o sdram bank 0 write enable xpcke o sdram bank 0 clock enable xpdqm[3:0] o sdram bank 0 data mask xpsclk io sdram bank 0 clock xpaddr[14:0] o sdram bank 0 address bus xpdata[31:0] o sdram bank 0 data bus
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-33 1.3.1.2 serial communication ? uart signal i/o description xuclk i uart 0 clock signal xurxd0 i uart 0 receives data input xuctsn0 i uart 0 clear to send input signal xutxd0 o uart 0 transmits data output xurtsn0 o uart 0 request to send output signal ? iic bus signal i/o description x2csda io iic-bus data x2cscl io iic-bus clock ? iis bus signal i/o description x2slrck io iis-bus channel select clock x2sdo o iis-bus serial data output x2sdi i iis-bus serial data input x2sclk io iis-bus serial clock x2scdclk o codec system clock ? spi bus signal i/o description xspissin[1:0] i spi chip select(only for slave mode) xspiclk io spi clock for channel 0 xspimiso io xspimiso is the ma ster data input line, when spi is configured as a master. when spi is configured as a slave, thes e pins reverse its role. for channel 0 xspimosi io xspimosi is the ma ster data output line, when spi is configured as a master. when spi is configured as a slave, thes e pins reverse its role. for channel 0 ? ? ac97 signal i/o description x97bitclk i ac-link bit clock(12.288mhz) from ac97 codec x97sdi i ac-link serial data input from ac97 codec x97resetn o ac-link reset to codec x97sync o ac-link frame synchronization (sam pling frequency 48khz) from ac97 controllor x97sdo o ac-link serial data output to ac97 codec
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-34 ? usb host signal i/o description xusdn[1:0] io data(?) from usb host xusdp[1:0] io data(+) from usb host ? usb device signal i/o description xuddn io data(?) for usb peripheral device xuddp io data(+) for usb peripheral device 1.3.1.3 parallel communication ? gpio signal i/o description xgpio[31:0] io general input/output ports ? modem interface (8-bit parallel) signal i/o description xmicsn i chip select, driven by the modem chip xmiwen i write enable, driven by the modem chip xmioen i read enable, driven by the modem chip xmiadr[10:0] i address bus, driven by the modem chip xmidata[7:0] io data bus, driven by the modem chip xmiirqn o interrupt request to the modem chip 1.3.1.4 image/video processing ? camera interface signal i/o description xcipclk i pixel clock, driven by the camera processor xcivsync i vertical sync, driv en by the camera processor xcihref i horizontal sync, driven by the camera processor xcicdata[7:0] i pixel data for cbcr in 16-bit mode, driven by the camera processor xciydata[7:0] i pixel data for ycbcr in 8-bit mode or for y in 16-bit mode, driven by the camera processor xciclk o master clock to the camera processor xcirstn o software reset to the camera processor
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-35 1.3.1.5 display control ? tft lcd display interface signal i/o description xvvd[17:0] o lcd pixel data output ports xvvclk o pixel clock signal xvvsync o vertical synchronous signal xvhsync o horizontal synchronous signal xvden o data enable signal 1.3.1.6 input devices ? analog-to-digital converter and touch screen interface signal i/o description xadcavref ai adc reference top xadcain[7:0] ai adc analog input 1.3.1.7 storage devices ? secure digital (sd) and memory stick interface signal i/o description xsddat[3:0] io sd/mmc card receive/transmit data xmspi i input port used for insertion/ extraction detect of memory stick xmssdio io sd/mmc card command signal port (default). if memorystick card enable, memory stick serial data in/out port xmssclko o sd/mmc card clock (default). if memory stick card enable, memorystick clock xmsbs o memorystick serial bus control signal
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-36 1.3.1.8 system management ? reset signal i/o description xsresetn i xsresetn suspends any operation in progress and places S3C24A0 into a known reset state. for a reset, xsresetn must be held to l level for at least 4 external clock after the processor power has been stabilized. xswresetn i system warm reset. reset the whole system while preserves the sdram contents xsrstoutn o for external device reset control (xsrstoutn = xsresetn & nwdtrst & sw_reset & xswresetn) ? clock signal i/o description xsmpllcap ao loop filter capacitor for main clock. xsupllcap ao loop filter capacitor for usb clock. xrtcxti ai 32 khz crystal input for rtc. xrtcxto ao 32 khz crystal output for rtc. xsxtin i crystal input for internal osc circuit. xsxtout o crystal input for internal osc circuit. xsextclk i external clock source. ? jtag signal i/o description xjtrstn i xjtrstn (tap controller reset) resets the tap controller at start. if debugger is used, a 10k pull-up resistor has to be connected. if debugger(black ice) is not used, trstn pin must be issued by a low active pulse(typically connected to xsresetn) xjtms i xjtms (tap controller mode select) cont rols the sequence of the tap controller?s states. a 10k pull-up resistor has to be connected to tms pin. xjtck i xjtck (tap controller clock) provides the clock input for the jtag logic. a 10k pull-up resistor must be connected to tck pin. xjrtck o xjrtck (tap controller returned clock) pr ovides the clock output for the jtag logic. xjtdi i xjtdi (tap controller data input) is the serial input for test instructions and data. a 10k pull-up resistor must be connected to tdi pin. xjtdo o xjtdo (tap controller data output) is t he serial output for test instructions and data.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-37 ? misc signal i/o description xgrefclksel[1:0] i clock source selection xgrefclksel determines how the clock is made. xgrefclksel[0] - ?0? : main clock source is from xsxtin, ?1? : main clock source is from xsextclk xgrefclksel[1] - ?0? : usb clock source is from xsxtin ?1? : usb clock source is from xsextclk xgtmode[3] i ?0? : pad jtag(selection of arm core boundary scan) ?1? : arm jtag(selection of S3C24A0 boundary scan) xgtmode[2:1] xgtmode[0] i these signals must be reserved ?00? ?0? : normal operation without nand boot ?1? : normal operation with nand boot xgbatfltn i probe for battery state (does not wake up at stop and sleep mode in case of low battery state) xgpwroffn o 1.2v core power on-off control signal xgmonhclk o hclk clock monitoring. hclk clock can be monitored through this pin when the clkmonon bit in the clkcon register is set. 1.3.1.9 power -supply groups ? vdd signal i/o description xxvddlogic p core logic vdd (1.2v) for internal logic xxvddalive p S3C24A0 reset block and port status register vdd (1.2v). it should be always supplied whether in normal mode or in stop and sleep mode. xxvddarm p core logic vdd (1.2v) for cpu xxvddmpll p S3C24A0 mpll analog and digital vdd (1.2 v). xxvddupll p S3C24A0 upll analog and digital vdd (1.2v) xxvddpadio p S3C24A0 i/o port vdd (3.3v) xxvddpadsdram p S3C24A0 sdram memory io vdd (3.3v) xxvddpadflash p S3C24A0 nflash memory io vdd (3.3v) xxvddpadusb p S3C24A0 usb io vdd (3.3v) xrtcvdd p rtc vdd (3.3v) (although rtc function is not used, this pin should be connected to power) xadcvdd p S3C24A0 adc vdd(3.3v)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-38 ? vss signal i/o description core logic vss for internal logic vss for S3C24A0 reset block and port status register core logic vss for cpu vss p S3C24A0 i/o port vss xxvsspadsdram p S3C24A0 sdram memory io vss xxvsspadflash p S3C24A0 flash memory io vss xxvsspadusb p S3C24A0 usb io vss xxvssmpll p S3C24A0 mpll analog and digital vss. xxvssupll p S3C24A0 upll analog and digital vss xrtcvss p rtc vss xadcvss p S3C24A0 adc vss note: 1. i/o means input/output. 2. ai/ao means analog input/output. 3. p means power.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-39 1.4 address map 1.4.1 address space assignment overview notes: 1. srom means rom or sram type memory. 2. sfr means special function register. [not using nand flash for boot rom] srom (xrcsn0) stepping stone (4kb, no cs) stepping stone (4kbytes) stepping stone (4kbytes) sdram (xpcsn0) srom (xrcsn0) srom (xrcsn1) srom (xrcsn2) srom (xrcsn1) srom (xrcsn2) srom (xrcsn1) [using nand flash for boot rom] 0x0800_0000 0x0000_0000 0x0400_0000 0x0c00_0000 0x1000_0000 sdram (xpcsn0) sdram (xpcsn0) 64mb 64mb 64mb 64mb sdram (xpcsn1) sdram (xpcsn1) sdram (xpcsn1) 128mb 128mb 0x1800_0000 ahb_s sfrs 0x2000_0000 0x4000_0000 apb sfrs ahb_i sfrs 0x4400_0000 0x4800_0000 0x5000_0000 64mb ahb_s sfrs apb sfrs ahb_i sfrs ahb_s sfrs apb sfrs ahb_i sfrs 64mb 128mb reserved 0xffff_ffff reserved reserved reserved reserved tmode[2:0] = 000 srom_bw[9] = 0 tmode[2:0] = 000 srom_bw[9] = 1 tmode[2:0] = 001 reserved reserved reserved assigned for special function registers assigned for sdram bank0/1 accessible region assigned for srom bank0/1/2 accessible region figure 1-2. address map
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-40 1.4.2 device specific address space ? ahb_s (system-side ahb bus) devices: base = 0x4000_0000 (just above 1gb), size = 64mb - physical address = base addres s + device offset + register offset device offset size (mb) group device note 0x00_0_0000 1 ahb_s systemctrl 0x01_0_0000 1 ahb_s reserved 0x02_0_0000 1 ahb_s intc 0x03_0_0000 1 ahb_s reserved 0x04_0_0000 1 ahb_s dma 0 0x05_0_0000 1 ahb_s dma 1 0x06_0_0000 1 ahb_s dma 2 0x07_0_0000 1 ahb_s dma 3 0x08_0_0000 4 ahb_s reserved 0x0c_0_0000 1 ahb_s memctrl 0x0d_0_0000 3 ahb_s reserved 0x10_0_0000 1 ahb_s usb host 0x11_0_0000 1 ahb_s modem if0 0x12_0_0000 6 ahb_s reserved 0x18_0_0000 1 ahb_s irda 0x19_0_0000 7 ahb_s reserved 0x20_0_0000 16 ahb_s ext ahb 0x30_0_0000 16 ahb_s reserved 0x40_0_0000 64 ahb_s apb devices through ahb to apb bridge 0x80_0_0000 128 ahb_s ahb_i devices through ahb to ahb bridge ? apb devices: base = 0x4000_0000 device offset size (mb) group device note 0x40_0_0000 1 apb pwm timer 0x41_0_0000 1 apb watch dog timer 0x42_0_0000 1 apb rtc 0x43_0_0000 1 apb reserved 0x44_0_0000 1 apb uart 0x45_0_0000 1 apb spi 0x46_0_0000 1 apb i2c 0x47_0_0000 1 apb i2s 0x48_0_0000 1 apb gpio 0x49_0_0000 1 apb keypad interface 0x4a_0_0000 1 apb usb device 0x4b_0_0000 5 apb reserved 0x50_0_0000 1 apb ac97 0x51_0_0000 7 apb reserved 0x58_0_0000 1 apb adc/touch screen 0x59_0_0000 7 apb reserved 0x60_0_0000 1 apb sd/mmc 0x61_0_0000 1 apb memory stick 0x62_0_0000 14 apb reserved 0x70_0_0000 16 apb reserved
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-41 ? ahb_i (the ahb bus for the image subsystem) devices: base = 0x4000_0000 offset (hex) size (mb) group device note 0x80_0_0000 4 ahb_i camera inteface 0x84_0_0000 4 ahb_i reserved 0x88_0_0000 4 ahb_i me 0x8c_0_0000 4 ahb_i mc 0x90_0_0000 4 ahb_i dct/q 0x94_0_0000 12 ahb_i reserved 0xa0_0_0000 1 ahb_i display controller 0xa1_0_0000 1 ahb_i video post processor 0xa2_0_0000 4 ahb_i reserved 0xa4_0_0000 10 ahb_i vlx 0xb0_0_0000 16 ahb_i reserved 0xc0_0_0000 16 ahb_i reserved 0xd0_0_0000 16 ahb_i reserved 0xe0_0_0000 16 ahb_i reserved 0xf0_0_0000 16 ahb_i reserved 1.4.3 internal registers the base of all devices internal registers = 0x4000_0000 1.4.3.1 external memory interface ? nand flash controller register name offset acc. unit read/ write function nfconf 0x0c0_0000 w r/w nand flash configuration nfcont 0x0c0_0004 nand flash control nfcmmd 0x0c0_0008 nand flash command nfaddr 0x0c0_000c nand flash address nfdata 0x0c0_0010 nand flash data nfmeccdata0 0x0c0_0014 nand flash main area ecc data reg.0 nfmeccdata1 0x0c0_0018 nand flash main area ecc data reg.1 nfmeccdata2 0x0c0_001c nand flash main area ecc data reg.2 nfmeccdata3 0x0c0_0020 nand flash main area ecc data reg.3 nfseccdata0 0x0c0_0024 nand flash spare area ecc data reg.1 nfseccdata1 0x0c0_0028 nand flash spare area ecc data reg.2 nfstat 0x0c0_002c r nand flash status
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-42 nfestat0 0x0c0_0030 nand flash ecc status 0 for i/o[7:0] nfestat1 0x0c0_0034 nand flash ecc status 1 for i/o[15:8] nfmecc0 0x0c0_0038 nand flash main area ecc reg.0 nfmecc1 0x0c0_003c nand flash main area ecc reg.1 nfsecc 0x0c0_0040 nand flash spare area ecc reg. nfsblk 0x0c0_0044 r/w nand flash start block address nfeblk 0x0c0_0048 nand flash end block address ? srom controller register name offset acc. unit read/ write function srom_bw 0x0c2_0000 w r/w srom bus width & wait control srom_bc0 0x0c2_0004 srom bank0 control register srom_bc1 0x0c2_0008 srom bank1 control register srom_bc2 0x0c2_000c srom bank2 control register ? sdram controller register name offset acc. unit read/ write function sdram_bankcfg 0x0c4_0000 w r/w sdram configuration sdram_bankcon 0x0c4_0004 sdram control sdram_refresh 0x0c4_0008 sdram refresh control ? bus matrix register name offset acc. unit read/ write function priority0 0x0ce_0000 w r/w priority control for sromc/nflashc priority1 0x0ce_0004 priority control for sdramc 1.4.3.2 general peripherals ? interrupt controller register name offset acc. unit read/ write function srcpnd 0x020_0000 w r/w interrupt request status intmod 0x020_0004 interrupt mode control intmsk 0x020_0008 interrupt mask control priority 0x020_000c irq priority control
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-43 intpnd 0x020_0010 interrupt request status intoffset 0x020_0014 r interrupt request source offset subsrcpnd 0x020_0018 r/w sub source pending intsubmsk 0x020_001c interrupt sub mask vecintmod 0x020_0020 vectored interrupt mode vecaddr 0x020_0024 r vectored mode address nvecaddr 0x020_0028 r/w non-vectored mode address var 0x020_002c r vector address register ? timer with pwm (pulse width modulation) register name offset acc. unit read/ write function tcfg0 0x400_0000 w r/w timer configuration tcfg1 0x400_0004 timer configuration tcon 0x400_0008 timer control tcntb0 0x400_000c timer count buffer 0 tcmpb0 0x400_0010 timer compare buffer 0 tcnto0 0x400_0014 r timer count observation 0 tcntb1 0x400_0018 r/w timer count buffer 1 tcmpb1 0x400_001c timer compare buffer 1 tcnto1 0x400_0020 r timer count observation 1 tcntb2 0x400_0024 r/w timer count buffer 2 tcmpb2 0x400_0028 timer compare buffer 2 tcnto2 0x400_002c r timer count observation 2 tcntb3 0x400_0030 r/w timer count buffer 3 tcmpb3 0x400_0034 timer compare buffer 3 tcnto3 0x400_0038 r timer count observation 3 tcntb4 0x400_003c r/w timer count buffer 4 tcnto4 0x400_0040 r timer count observation 4 ? 16-bit watchdog timer. register name offset acc. unit read/ write function wtcon 0x410_0000 w r/w watch-dog timer mode wtdat 0x410_0004 watch-dog timer data wtcnt 0x410_0008 watch-dog timer count 4-ch dma controller.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-44 register name offset acc. unit read/ write function disrc0 0x040_0000 w r/w dma 0 initial source disrcc0 0x040_0004 dma 0 initial source control didst0 0x040_0008 dma 0 initial destination didstc0 0x040_000c dma 0 initial destination control dcon0 0x040_0010 dma 0 control dstat0 0x040_0014 r dma 0 count dcsrc0 0x040_0018 dma 0 current source dcdst0 0x040_001c dma 0 current destination dmasktrig0 0x040_0020 w r/w dma 0 mask trigger disrc1 0x050_0000 dma 1 initial source disrcc1 0x050_0004 dma 1 initial source control didst1 0x050_0008 dma 1 initial destination didstc1 0x050_000c dma 1 initial destination control dcon1 0x050_0010 dma 1 control dstat1 0x050_0014 r dma 1 count dcsrc1 0x050_0018 dma 1 current source dcdst1 0x050_001c w dma 1 current destination dmasktrig1 0x050_0020 r/w dma 1 mask trigger disrc2 0x060_0000 dma 2 initial source disrcc2 0x060_0004 dma 2 initial source control didst2 0x060_0008 dma 2 initial destination didstc2 0x060_000c dma 2 initial destination control dcon2 0x060_0010 dma 2 control dstat2 0x060_0014 r dma 2 count dcsrc2 0x060_0018 w dma 2 current source dcdst2 0x060_001c dma 2 current destination dmasktrig2 0x060_0020 r/w dma 2 mask trigger disrc3 0x070_0000 w r/w dma 3 initial source disrcc3 0x070_0004 dma 3 initial source control didst3 0x070_0008 dma 3 initial destination didstc3 0x070_000c dma 3 initial destination control dcon3 0x070_0010 dma 3 control dstat3 0x070_0014 r dma 3 count dcsrc3 0x070_0018 dma 3 current source dcdst3 0x070_001c dma 3 current destination dmasktrig3 0x070_0020 r/w dma 3 mask trigger
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-45 ? rtc (real time clock) register name offset acc. unit read/ write function rtccon 0x420_0040 b r/w rtc control ticint 0x420_0044 tick time count rtcalm 0x420_0050 rtc alarm control almsec 0x420_0054 alarm second almmin 0x420_0058 alarm minute almhour 0x420_005c alarm hour almdate 0x420_0060 alarm day almmon 0x420_0064 alarm month almyear 0x420_0068 alarm year rtcrst 0x420_006c rtc round reset bcdsec 0x420_0070 bcd second bcdmin 0x420_0074 bcd minute bcdhour 0x420_0078 bcd hour bcddate 0x420_007c bcd day bcdday 0x420_0080 bcd date bcdmon 0x420_0084 bcd month bcdyear 0x420_0088 bcd year 1.4.3.3 serial communication ? uart register name offset acc. unit read/ write function ulcon0 0x440_0000 w r/w uart 0 line control ucon0 0x440_0004 uart 0 control ufcon0 0x440_0008 uart 0 fifo control umcon0 0x440_000c uart 0 modem control utrstat0 0x440_0010 r uart 0 tx/rx status uerstat0 0x440_0014 uart 0 rx error status ufstat0 0x440_0018 uart 0 fifo status umstat0 0x440_001c uart 0 modem status utxh0 0x440_0020 b w uart 0 transmission hold urxh0 0x440_0024 r uart 0 receive buffer ubrdiv0 0x440_0028 w r/w uart 0 baud rate divisor ulcon1 0x440_4000 w r/w uart 1 line control
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-46 ucon1 0x440_4004 uart 1 control ufcon1 0x440_4008 uart 1 fifo control umcon1 0x440_400c uart 1 modem control utrstat1 0x440_4010 r uart 1 tx/rx status uerstat1 0x440_4014 uart 1 rx error status ufstat1 0x440_4018 uart 1 fifo status umstat1 0x440_401c uart 1 modem status utxh1 0x440_4020 b w uart 1 transmission hold urxh1 0x440_4024 r uart 1 receive buffer ubrdiv1 0x440_4028 w r/w uart 1 baud rate divisor ? iic-bus interface register name offset acc. unit read/ write function iiccon 0x460_0000 w r/w iic control iicstat 0x460_0004 iic status iicadd 0x460_0008 iic address iicds 0x460_000c iic data shift iicsdadly 0x460_0010 1-bit sda output delay ? iis-bus interface register name offset acc. unit read/ write function iiscon 0x470_0000 w r/w iis control iismod 0x470_0004 w iis mode iispsr 0x470_0008 w iis prescaler iisfcon 0x470_000c w iis fifo control iisfifo 0x470_0010 hw iis fifo entry ? spi interface register name offset acc. unit read/ write function spcon0 0x450_0000 w r/w spi channel 0 control spsta0 0x450_0004 r spi channel 0 status sppin0 0x450_0008 r/w spi channel 0 pin control sppre0 0x450_000c spi channel 0 baud rate prescaler sptdat0 0x450_0010 spi channel 0 tx data sprdat0 0x450_0014 r spi channel 0 rx data
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-47 spcon1 0x450_0020 r/w spi channel 1 control spsta1 0x450_0024 r spi channel 1 status sppin1 0x450_0028 r/w spi channel 1 pin control sppre1 0x450_002c spi channel 1 baud rate prescaler sptdat1 0x450_0030 spi channel 1 tx data sprdat1 0x450_0034 r spi channel 1 rx data ? ac97 audio-codec interface register name offset acc. unit read/ write function ac_glbctrl 0x500_0000 w r/w ac97 global control ac_glbstat 0x500_0004 r ac97 global status ac_codec_cmd 0x500_0008 r/w ac97 codec command ac_codec_stat 0x500_000c r ac97 codec status ac_pcm_addr 0x500_0010 r ac97 pcm out/in channel fifo address ac_micaddr 0x500_0014 r ac97 mic in channel fifo address ac_pcmdata 0x500_0018 r/w ac97 pcm out/in channel fifo data ac_micdata 0x500_001c r/w ac97 mic in channel fifo data ? usb host register name offset acc. unit read/ write function hcrevision 0x100_0000 w control and status group hccontrol 0x100_0004 hccommonstatus 0x100_0008 hcinterruptstatus 0x100_000c hcinterruptenable 0x100_0010 hcinterruptdisable 0x100_0014 hchcca 0x100_0018 memory pointer group hcperiodcuttented 0x100_001c hccontrolheaded 0x100_0020 hccontrolcurrented 0x100_0024 hcbulkheaded 0x100_0028 hcbulkcurrented 0x100_002c hcdonehead 0x100_0030 hcrminterval 0x100_0034 frame counter group hcfmremaining 0x100_0038
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-48 hcfmnumber 0x100_003c hcperiodicstart 0x100_0040 hclsthreshold 0x100_0044 hcrhdescriptora 0x100_0048 root hub group hcrhdescriptorb 0x100_004c hcrhstatus 0x100_0050 hcrhportstatus1 0x100_0054 hcrhportstatus2 0x100_0058 ? usb device register name offset acc. unit read/ write function func_addr_reg 0x4a0_0140 b r/w function address pwr_reg 0x4a0_0144 power management ep_int_reg 0x4a0_0148 ep interrupt pending and clear usb_int_reg 0x4a0_0158 usb interrupt pending and clear ep_int_en_reg 0x4a0_015c interrupt enable usb_int_en_reg 0x4a0_016c interrupt enbale frame_num1_reg 0x4a0_0170 r frame number lower byte index_reg 0x4a0_0178 r/w register index ep0_csr 0x4a0_0184 endpoint 0 status in_csr1_reg 0x4a0_0184 in endpoint control status in_csr2_reg 0x4a0_0188 in endpoint control status maxp_reg 0x4a0_0180 endpoint max packet out_csr1_reg 0x4a0_0190 out endpoint control status out_csr2_reg 0x4a0_0194 out endpoint control status out_fifo_cnt1_reg 0x4a0_0198 r endpoint out write count out_fifo_cnt2_reg 0x4a0_019c endpoint out write count ep0_fifo 0x4a0_01c0 r/w endpoint 0 fifo ep1_fifo 0x4a0_01c4 endpoint 1 fifo ep2_fifo 0x4a0_01c8 endpoint 2 fifo ep3_fifo 0x4a0_01cc endpoint 3 fifo ep4_fifo 0x4a0_01d0 endpoint 4 fifo ep1_dma_con 0x4a0_0200 ep1 dma interface control ep1_dma_unit 0x4a0_0204 ep1 dma tx unit counter ep1_dma_fifo 0x4a0_0208 ep1 dma tx fifo counter ep1_dma_ttc_l 0x4a0_020c ep1 dma total tx counter
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-49 ep1_dma_ttc_m 0x4a0_0210 ep1 dma total tx counter ep1_dma_ttc_h 0x4a0_0214 ep1 dma total tx counter ep2_dma_con 0x4a0_0218 b r/w ep2 dma interface control ep2_dma_unit 0x4a0_021c ep2 dma tx unit counter ep2_dma_fifo 0x4a0_0220 ep2 dma tx fifo counter ep2_dma_ttc_l 0x4a0_0224 ep2 dma total tx counter ep2_dma_ttc_m 0x4a0_0228 ep2 dma total tx counter ep2_dma_ttc_h 0x4a0_022c ep2 dma total tx counter ep3_dma_con 0x4a0_0240 ep3 dma interface control ep3_dma_unit 0x4a0_0244 ep3 dma tx unit counter ep3_dma_fifo 0x4a0_0248 ep3 dma tx fifo counter ep3_dma_ttc_l 0x4a0_024c ep3 dma total tx counter ep3_dma_ttc_m 0x4a0_0250 ep3 dma total tx counter ep3_dma_ttc_h 0x4a0_0254 ep3 dma total tx counter ep4_dma_con 0x4a0_0258 ep4 dma interface control ep4_dma_unit 0x4a0_025c ep4 dma tx unit counter ep4_dma_fifo 0x4a0_0260 ep4 dma tx fifo counter ep4_dma_ttc_l 0x4a0_0264 ep4 dma total tx counter ep4_dma_ttc_m 0x4a0_0268 ep4 dma total tx counter ep4_dma_ttc_h 0x4a0_026c ep4 dma total tx counter ? irda register name offset acc. unit read/ write function irda _cnt 0x180_0000 w r/w irda control r irda_mdr 0x180_0004 irda mode definition irda_cnf 0x180_0008 irda interrupt / dma configuration irda _ier 0x180_000c irda interrupt enable irda _iir 0x180_0010 r irda interrupt identification irda _lsr 0x180_0014 irda line status irda _fcr 0x180_0018 r/w irda fifo control irda _plr 0x180_001c irda preamble length irda_rbr 0x180_0020 irda receiver & transmitter buffer irda_txno 0x180_0024 r the total number of data bytes remained in tx fifo irda_rxno 0x180_0028 the total number of data bytes remained in rx fifo irda _txfll 0x180_002c r/w irda transmit frame-length register low
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-50 irda _txflh 0x180_0030 irda trans mit frame-length register high irda _rxfll 0x180_0034 irda re ceive frame-length register low irda _rxflh 0x180_0038 irda rece ive frame-length register high 1.4.3.4 parallel communication ? modem interface register name offset acc. unit read/ write function int2ap 0x118_0000 w r/w interrupt request to ap register int2mdm 0x118_0004 interrupt request to modem register ? gpio register name offset acc. unit read/ write function gpcon_u 0x480_0000 w r/w gpio ports configuration register gpcon_m 0x480_0004 gpio ports configuration register gpcon_l 0x480_0008 gpio ports configuration register gpdat 0x480_000c gpio ports data register gppu 0x480_0010 gpio ports pull-up control register extintc0 0x480_0018 external interrupt control register 0 extintc1 0x480_001c external interrupt control register 1 extintc2 0x480_0020 external interrupt control register 2 eintflt0 0x480_0024 external interrupt filter control register 0 eintflt1 0x480_0028 external interrupt filter control register 1 eintmask 0x480_0034 external interupt mask register eintpend 0x480_0038 external interupt pending register peripu 0x480_0040 peri. ports pull-up control register alivecon 0x480_0044 alive control register gpdat_sleep 0x480_0048 gpio output data for sleep mode gpoen_sleep 0x480_004c gpio output enable control for sleep mode gppu_sleep 0x480_0050 gpio pull-up control register for sleep mode peridat_sleep0 0x480_0054 peri. ports out put data control register 0 for sleep mode peridat_sleep1 0x480_0058 peri. ports out put data control register 1 for sleep mode perioen_sleep0 0x480_005c peri. ports out put control register 0 for sleep mode perioen_sleep1 0x480_0060 peri. ports out put control register 1 for sleep mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-51 peripu_sleep 0x480_0064 peri. ports pull-up control register for slee mode rstcnt 0x480_0068 reset count compare register gpram0~15 0x480_0080 ~0x480_00bc general purpose ram array 1.4.3.5 image/video processing ? camera interface register name offset acc. unit read/ write function cisrcfmt 0x800_0000 w r/w input source format ciwdofst 0x800_0004 window offset register cigctrl 0x800_0008 global control register cicoysa1 0x800_0018 y 1 st frame start address for codec dma cicoysa2 0x800_001c y 2 nd frame start address for codec dma cicoysa3 0x800_0020 y 3 rd frame start address for codec dma cicoysa4 0x800_0024 y 4 th frame start address for codec dma cicocbsa1 0x800_0028 cb 1 st frame start address for codec dma cicocbsa2 0x800_002c cb 2 nd frame start address for codec dma cicocbsa3 0x800_0030 cb 3 rd frame start address for codec dma cicocbsa4 0x800_0034 cb 4 th frame start address for codec dma cicocrsa1 0x800_0038 cr 1 st frame start address for codec dma cicocrsa2 0x800_003c cr 2 nd frame start address for codec dma cicocrsa3 0x800_0040 cr 3 rd frame start address for codec dma cicocrsa4 0x800_0044 cr 4 th frame start address for codec dma cicotrgfmt 0x800_0048 target image format of codec dma cicoctrl 0x800_004c codec dma control related cicoscpreratio 0x800_0050 codec pre-scaler ratio control cicoscpredst 0x800_0054 codec pre-scaler destination format cicoscctrl 0x800_0058 codec main-scaler control cicotarea 0x800_005c codec pre-scaler destination format cicostatus 0x800_0064 r codec path status ciprclrsa1 0x800_006c r/w rgb 1 st frame start address for preview dma ciprclrsa2 0x800_0070 rgb 2 nd frame start address for preview dma ciprclrsa3 0x800_0074 rgb 3 rd frame start address for preview dma
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-52 ciprclrsa4 0x800_0078 rgb 4 th frame start address for preview dma ciprtrgfmt 0x800_007c target image format of preview dma ciprctrl 0x800_0080 preview dma control related ciprscpreratio 0x800_0084 preview pre-scaler ratio control ciprscpredst 0x800_0088 preview pre-scaler destination format ciprscctrl 0x800_008c preview main-scaler control ciprtarea 0x800_0090 preview pre-scaler destination format ciprstatus 0x800_0098 r preview path status ciimgcpt 0x800_00a0 r/w image capture enable command ? video post register name offset acc. unit read/ write function mode 0xa10_0000 w r/w mode register [9:0] prescale_ratio 0xa10_0004 pre-scale ratio for vertical and horizontal. prescaleimgsize 0xa10_0008 pre-scaled image size srcimgsize 0xa10_000c source image size mainscale_h_ratio 0xa10_0010 main scale ratio along to horizontal direction mainscale_v_ratio 0xa10_0014 main scale ratio along to vertical direction dstimgsize 0xa10_0018 destination image size prescale_shfactor 0xa10_001c pre-scale shift factor addrstart_y 0xa10_0020 dma start address for y or rgb component addrstart_cb 0xa10_0024 dma start address for cb component addrstart_cr 0xa10_0028 dma start address for cr component addrstart_rgb 0xa10_002c dma start address for rgb component addrend_y 0xa10_0030 dma end address for y or rgb component addrend_cb 0xa10_0034 dma end address for cb component addrend_cr 0xa10_0038 dma end address for cr component addrend_rgb 0xa10_003c dma end address for rgb component offset_y 0xa10_0040 offset of y component for fetching source image offset_cb 0xa10_0044 offset of cb component for fetching source image offset_cr 0xa10_0048 offset of cr com ponent for fetching source image offset_rgb 0xa10_004c offset of rgb component for restoring destination image
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-53 me register name offset acc. unit read/ write function me_cfsa 0x880_0000 current frame start address register me_pfsa 0x880_0004 previous frame start address register me_mvsa 0x880_0008 motion vector start address register me_cmnd 0x880_000c command register me_stat_swr 0x880_0010 status & s/w reset register me_cnfg 0x880_0014 configuration register me_imgfmt 0x880_0018 w r/w image format register ? mc register name offset acc. unit read/ write function mc_pfysa_enc 0x8c0_0000 previous frame y start address register for the encoder mc_cfysa_enc 0x8c0_0004 mced frame y start address register for the encoder mc_pfysa_dec 0x8c0_0008 previous frame y start address register for the decoder mc_cfysa_dec 0x8c0_000c mced frame y start address register for the decoder mc_pfcbsa_enc 0x8c0_0010 previous frame cb start address register for the encoder mc_pfcrsa_enc 0x8c0_0014 previous frame cr start address register for the encoder mc_cfcbsa_enc 0x8c0_0018 mced frame cb start address register for the encoder mc_cfcrsa_enc 0x8c0_001c mced frame cr start address register for the encoder mc_pfcbsa_dec 0x8c0_0020 previous frame cb start address register for the decoder mc_pfcrsa_dec 0x8c0_0024 previous frame cr start address register for the decoder mc_cfcbsa_dec 0x8c0_0028 mced frame cb start address register for the decoder mc_cfcrsa_dec 0x8c0_002c mced frame cr start address register for the decoder mc_mvsa_enc 0x8c0_0030 w r/w motion vector start address register for the encoder
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-54 mc_mvsa_dec 0x8c0_0034 motion vector start address register for the decoder mc_cmnd 0x8c0_0038 command register mc_stat_swr 0x8c0_003c status & s/w reset register mc_cnfg 0x8c0_0040 configuration register mc_imgfmt 0x8c0_0044 image format register ? dctq register name offset acc. unit read/ write function saycf 0x900_0000 w r/w current frame luminance start address sacbcf 0x900_0004 current frame cb start address sacrcf 0x900_0008 current frame cr start address sayrf 0x900_000c reconstruction frame luminance start address sacbrf 0x900_0010 reconstruction frame cb start address sacrrf 0x900_0014 reconstruction frame cr start address saydqf 0x900_0018 dctqed fram e luminance start address sacbdqf 0x900_001c dctqed frame cb start address sacrdqf 0x900_0020 dctqed frame cr start address saqp 0x900_0024 qp start address imgsize 0x900_0028 image horizontal and vertical pixel number shq 0x900_002c short header quantization mode dctqctrl 0x900_0034 control register ? vlx register name offset acc. unit read/ write function vlx_common1 0x940_0000 w r/w vlx common control register1 vlx_framestarty 0x940_0004 y coeff. start address vlx_framestartcb 0x940_0008 cb coeff. frame start address vlx_framestartcr 0x940_000c cr coeff. frame start address vlc_con1 0x940_0010 control register in vlc mode vlc_con2 0x940_0014 reserved
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-55 vlc_con3 0x940_0018 vlc result external address vlc_con4 0x940_001c reserved vld_con1 0x940_0020 control register in vld mode vld_con2 0x940_0024 vlced bit stream start address vld_con3 0x940_0028 reserved vlx_out1 0x940_002c r vlx output information register 1 vlx_out2 0x940_0030 vlx output information register 2 1.4.3.6 display control ? tft lcd controller register offset acc. unit r/w function lcdcon1 0xa00_0000 w r/w lcd control 1 lcdcon2 0xa00_0004 r/w lcd control 2 lcdtcon1 0xa00_0008 r/w lcd time control 1 lcdtcon2 0xa00_000c r/w lcd time control 2 lcdtcon3 0xa00_0010 r/w lcd time control 3 lcdosd1 0xa00_0014 r/w lcd osd control register lcdosd2 0xa00_0018 r/w foreground image(osd image) left top position set lcdosd3 0xa00_001c r/w foreground image(osd image) right bottom position set lcdsaddrb1 0xa00_0020 r/w frame buffer start address 1 ( background buffer 1) lcdsaddrb2 0xa00_0024 r/w frame buffer start address 2 ( background buffer 2) lcdsaddrf1 0xa00_0028 r/w frame buffer start address 1 ( foreground buffer 1) lcdsaddrf2 0xa00_002c r/w frame buffer start address 2 ( foreground buffer 2) lcdeaddrb1 0xa00_0030 r/w frame buffer end address 1 ( background buffer 1) lcdeaddrb2 0xa00_0034 r/w frame buffer end address 2 ( background buffer 2) lcdeaddrf1 0xa00_0038 r/w frame buffer end address 1 ( foreground buffer 1) lcdeaddrf2 0xa00_003c r/w frame buffer end address 2 ( foreground buffer 2) lcdvscrb1 0xa00_0040 r/w virtual sc reen offsize and pagewidth ( background buffer 1) lcdvscrb2 0xa00_0044 r/w virtual sc reen offsize and pagewidth ( background buffer 2) lcdvscrf1 0xa00_0048 r/w virtual sc reen offsize and pagewidth ( foreground buffer 1) lcdvscrf2 0xa00_004c r/w virtual sc reen offsize and pagewidth ( foreground buffer 2) lcdintcon 0xa00_0050 r/w lcd interrupt control lcdkeycon 0xa00_0054 r/w color key control 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-56 lcdkeyval 0xa00_0058 r/w color key control 2 lcdbgcon 0xa00_005c r/w back-ground color control lcdfgcon 0xa00_0060 r/w fore-ground color control lcddithcon 0xa00_0064 r/w lcd dithering control for active matrix 1.4.3.7 input devices ? keypad interface register name offset acc. unit read/ write function keydat 0x490_0000 w r/w the data register for keypad input keyintc 0x490_0004 keypad input ports interrupt control keyflt0 0x490_0008 key pad i nput filter control keyflt1 0x490_000c key pad input filter control keyman 0x490_0010 keypad manual scan control ? analog-to-digital converter and touch screen interface register name offset acc. unit read/ write function adccon 0x580_0000 w r/w adc control adctsc 0x580_0004 adc touch screen control adcdly 0x580_0008 adc start or interval delay adcdax 0x580_000c r adc conversion data register x adcday 0x580_0010 adc conversion data register y 1.4.3.8 storage devices ? sd and sdio / mmc register name offset acc. unit read/ write function sdicon 0x600_0000 w r/w sdi control sdipre 0x600_0004 sdi buad rate prescaler sdicarg 0x600_0008 sdi command argument sdiccon 0x600_000c sdi command control sdicsta 0x600_0010 r/(c) sdi command status sdirsp0 0x600_0014 r sdi response sdirsp1 0x600_0018 sdi response sdirsp2 0x600_001c sdi response sdirsp3 0x600_0020 sdi response sdidtimer 0x600_0024 r/w sdi data / busy timer
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor p reliminary product overview 1-57 sdibsize 0x600_0028 sdi block size sdidcon 0x600_002c w r/w sdi data control sdidcnt 0x600_0030 r sdi data remain counter sdidsta 0x600_0034 r/(c) sdi data status sdifsta 0x600_0038 r/(c) sdi fifo status sdiimsk 0x600_003c r/w sdi interrupt mask sdidat0 0x600_0040 b,hw,w sdi data0 sdidat1 0x600_0044 w sdi data1 sdidat2 0x600_0048 sdi data2 sdidat3 0x600_004c sdi data3 ? memory stick register name offset acc. unit read/ write function mspre 0x610_0000 w r/w prescaler control msfintcon 0x610_0004 fif o interrupt control tp_cmd 0x610_8000 transfer protocol command ctrl_sta 0x610_8004 command and status dat_fifo 0x610_8008 data fifo intctrl_sta 0x610_800c interrupt control and status ins_con 0x610_8010 ins port control acmd_con 0x610_8014 auto command and polarity control atp_cmd 0x610_8018 auto transfer protocol command 1.4.3.8 system management ? pll clock control and power management register name offset acc. unit read/ write function locktime 0x000_0000 w r/w pll lock time counter oscwset 0x000_0004 osc settle-down wait time setting mpllcon 0x000_0010 mpll configuration upllcon 0x000_0014 upll configuration clkcon 0x000_0020 clock generator control clksrc 0x000_0024 slow clock control clkdivn 0x000_0028 clock divider control pwrman 0x000_0030 power management softreset 0x000_0038 software reset
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. preliminary product overview S3C24A0 risc microprocessor 1-58 important notes about s3 c24a0 special registers 1. the special registers have to be accessed by the recommended access unit. 2. all registers except adc registers, rtc registers and uart registers must be read/written in word unit (32bit) at little/big endian. 3. it is very important that the adc registers, rtc registers and uart registers be read/wr itten by the specified access unit and the specified address. moreover, one must carefully consider which endian mode is used. 4. w : 32-bit register, which must be acce ssed by ldr/str or int type pointer(int *). hw : 16-bit register, which must be accessed by ldrh/strh or short int type pointer(short int *). b : 8-bit register, which must be accessed by ldrb/strb or char type pointer(char int *). .
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor srom controller 2-1 srom controller(preliminary) overview S3C24A0 support external 16-bit bus for nand flash/ nor flash/ prom/ sram external memory. it?s not shared with sdram bus and support up to 3 bank for one controller. from now on, we call this controller as srom controller. below figure show the address map configuration of s3 c24a0 srom controller. S3C24A0 srom controller has 3 kinds of configuration. if user want to us e nand boot loader, it?ll be selected the third configuration which stepping stone (sram 4kb) is on the 0x00000000. and if user want to use rom type boot, it?ll be selected the first or second configuration by selecting s fr (special function register) of srom controller. in this case user can use nand flash memory for other usage. at the first configuration, stepping stone is used just for buffer of any master. notes: 1. srom means rom or sram type memory. 2. sfr means special function register. [not using nand flash for boot rom] srom (bank0, xrcsn0) sram buffer (4kb, no cs) stepping stone (4kbytes) stepping stone (4kbytes) sdram (bank0/1) srom srom (bank1, xrcsn1) srom (bank2, xrcsn2) srom srom srom [using nand flash for boot rom] 0x0800_0000 0x0000_0000 0x0400_0000 0x0c00_0000 0x1000_0000 sdram sdram 64mb 64mb 64mb 64mb 256mb 0x2000_0000 0x4000_0000 ahb/apb sfrs 0x5000_0000 256mb reserved 0xffff_ffff reserved reserved reserved reserved tmode[2:0] = 000 srom_bw[9] = 0 tmode[2:0] = 000 srom_bw[9] = 1 tmode[2:0] = 001 reserved reserved reserved assigned for special function registers assigned for sdram bank0/1 accessible region assigned for srom bank0/1/2 accessible region (bank2, xrcsn2) (bank0, xrcsn0) (bank1, xrcsn1) (bank1, xrcsn1) (bank0/1) (bank0/1) ahb/apb sfrs ahb/apb sfrs figure 2-1. srom controller address mapping
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. srom controller S3C24A0 risc microprocessor 2-2 feature - supports sram, various roms and nor flash memory - supports only 8 or 16-bit data bus - address space : up to 64mb per bank - supports 3 banks (xrcsn[2:0]) boot by nand flash memory : xrcsn0?s owner is not srom controller but nand controller. boot by other memory (nor flash or rom): xrcsn2? s owner is either srom controller or nand controller (user can choose it by setting sfr). - fixed memory bank start address - external wait to extend the bus cycle - support byte, half-word and word access for external memory block diagram srom decoder sfr control & state machine srom i/f singal generato n ahb i/f for srom sfr ahb i/f for srom mem srom mem i/f figure 2-2 srom controller block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor srom controller 2-3 function description srom controller support srom interface for bank0 to bank2. in case of nand boot, srom controller can?t control bank0 because of its mastership is on nand flash controller. in case of rom boot, as it mentioned before, it is possible that bank2?s master is nand flash controller by setting of users. sram/rom/ nor flash/ nand flash sram/rom/ nor flash sram/rom/ nor flash /nand flash bank0 bank2 bank1 memory bus #1 srom controller address-bus : 26-bit data-bus : 8/16 figure 2-3 memory interface block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. srom controller S3C24A0 risc microprocessor 2-4 xrwaitn pin operation if the wait corresponding to each memory bank is enabled, the xroen duration should be prolonged by the external xrwaitn pin while the memory bank is active. xrwaitn is checked from tacc-1. the xroen will be deasserted at the next clock after s ampling xrwaitn is high. the xrwen signal have the same relation with xroen. tacs tcos tacc=4 hclk xraddr [25:0] xrcsn [2:0] xroen xrwaitn xrdata [15:0] (r) delayed sampling xrwaitn figure 2-4 xrwaitn pin operation
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor srom controller 2-5 programmable access cycle write to read waveform tcoh tcos tacs hclk xraddr [25:0] xrcsn [2:0] xroen xrwen xrnwbe [1:0] xrdata [15:0] (r) xrdata [15:0] (w) t acc tcah tacs = 1 cycle tcos = 1 cycle tacc = 2 cycles tcoh = 1 cycle tcah = 2 cycles figure 2-4 programmable access cycle
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. srom controller S3C24A0 risc microprocessor 2-6 special function registers srom bus width & wait contrl register(srom_bw) register address r/w description reset value srom_bw 0x40c20000 r/w srom bus width & wait control 0x000x srom_bw bit description initial state reserved [15:9] reserved 0x00 banknum [9] 0 = xrcsn2?s owner is srom controller (in this case stepping stone is just used as 4kb sram buffer) 1 = xrcsn2?s owner is nand flash controller 0x00 st2 [8] this bit determines sram for using ub/lb for bank2 0 = not using ub/lb (xrnwbe[1:0] is dedicated nwbe[1:0]) 1 = using ub/lb (xrnwbe[1:0] is dedicated nbe[1:0] 0 ws2 [7] this bit determines wait status for bank2 0 = wait disable 1 : wait enable 0 dw2 [6] indicates data bus width for bank2 0 = 8-bit 1 : 16-bit 0 st1 [5] this bit determines sram for using ub/lb for bank1 0 = not using ub/lb (xrnwbe[1:0] is dedicated nwbe[1:0]) 1 = using ub/lb (xrnwbe[1:0] is dedicated nbe[1:0] 0 ws1 [4] this bit determines wait status for bank1 0 = wait disable 1 : wait enable 0 dw1 [3] indicates data bus width for bank1 0 = 8-bit 1 : 16-bit 0 st0 [2] this bit determines sram for using ub/lb for bank0 0 = not using ub/lb (xrnwbe[1:0] is dedicated nwbe[1:0]) 1 = using ub/lb (xrnwbe[1:0] is dedicated nbe[1:0] 0 ws0 [1] this bit determines wait status for bank0 0 = wait disable 1 : wait enable 0 dw0 [0] indicates data bus width for bank0 (read only) 0 : 8-bit 1 : 16-bit h/w set * dw0 is read only. the value is written by external configuration pin(xfnfbw)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor srom controller 2-7 srom bank control register (srom_bc : xrcsn0 ~ xrcsn2) register address r/w description reset value srom_bc0 0x40c20004 r/w srom bank0 control register 0x0700 srom_bc1 0x40c20008 r/w srom bank1 control register 0x0700 srom_bc2 0x40c2000c r/w srom bank2 control register 0x0700 srom_bcn bit description initial state tacs [15:14] adress set-up before xrcsn[2:0] 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks 00 tcos [13:12] chip selection set-up xroen 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks 00 reserved [11] reserved 0 tacc [10:8] access cycle 000 = 2 clock 001 = 3 clocks 010 = 4 clocks 011 = 10 clocks 100 = 12 clocks 101 = 14 clocks 110 = 16 clock 111 = 20 clocks 111 tcoh [7:6] chip selection hold on xroen 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks 00 tcah [5:4] address holding time after xrcsn[2:0] 00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks 00 reserved [3:0] reserved 0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdram controller 3-1 3 sdram controller (preliminary) overview the S3C24A0 sdram controller has the following features: ? sdram ? supports 16-bit or 32-bit data bus ? supports 2 banks: xpcsn[1:0] ? 16-bit refresh timer ? self refresh mode ? programmable cas latency ? provide write buffer (4word size x2) ? provide long burst(incr8,16 & wrap8,16) transfer ? provide power down mode ? support mobile sdram ? support extended mrs set (emrs) - ds , tscr, pasr
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdram controller s3c24 a0 risc microprocessor 3-2 selection of sdram we recommanded select one of the sdram configurations in table 3-1. and, each two banks should have same bus width. table 3-1. supported sdram configuration total size bus width base component memory configuration bank address 4mb x32 16mb (512kbit x 16bit x 2bank) x 2ea a13 8mb 64mb (512k x 32 x 4) x 1 a[14:13] 16mb (1m x 8 x 2) x 4 a13 16mb 128mb (1m x 32 x 4) x 1 a[14:13] 64mb (1m x 16 x 4) x 2 a[14:13] 32mb 256mb (2m x 32 x 4) x 1 a[14:13] 128mb (2m x 16 x 4) x 2 a[14:13] 64mb (2m x 8 x 4) x 4 a[14:13] 64mb 256mb (4m x 16 x 4) x 2 a[14:13] 128mb (4m x 8 x 4) x 4 a[14:13] 512mb (4m x 32 x 4) x 1 a[14:13] 128mb 256mb (8m x 8 x 4) x 4 a[14:13] 512mb (8m x 16 x 4) x 2 a[14:13] 2mb x16 16mb (512k x 16 x 2) x 1 a13 4mb 16mb (1m x 8 x 2) x 2 a13 8mb 64mb (1m x 16 x 4) x 1 a[14:13] 16mb 128mb (2m x 16 x 4) x 1 a[14:13] 64mb (2m x 8 x 4) x 2 a[14:13] 32mb 256mb (4m x 16 x 4) x 1 a[14:13] 128mb (4m x 8 x 4) x 2 a[14:13] 64mb 256mb (8m x 8 x 4) x 2 a[14:13] 512mb (8m x 16 x 4) x 1 a[14:13] self refresh the S3C24A0 provides the auto refresh and self refres h command to sustain the contents of sdram. the auto refresh is issued to sdram periodically when refresh time r is expired. the self refresh is entered and exited by request of on-chip power manager.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdram controller 3 -3 sdram initialization sequence on power-on reset, software must initialize the memory controller and each of the sdram connected to the controller. refer to the sdram data sheet for the st art up procedure, and examples sequence is given below: 1. wait 200us to allow sdram power and clock stabilize. 2. program the init[1:0] to ?01b?. this automatica lly issues a pall(pre-charge all) cammand to the sdram. 3. write ? 0x20 ? into the refresh timer register. th is provides a refresh cycle every 32 -clock cycles. 4. wait for a time period equivalent to 128 -clock cycles ( 4 refresh cycles). 5. program the normal operational va lue into the refresh timer.. 6. program the configurat ion registers to their normal operation values. 7. program the init[1:0] to ?10b?. this automat ically issues a mrs command to the sdram. 8. mobile only program the init[1:0] to ?11b?. this aut omatically issues a emrs command to the sdram. 9. program the init[1:0] to ?00b?. the controller enters the normal mode. 10. the sdram is now ready for normal operation. note : if you issue mrs after issuing emrs, emrs value will be rese t . so you have to issue emrs after issuing mrs.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdram controller s3c24 a0 risc microprocessor 3-4 sdram memory interface examples xpaddr0 xpaddr1 xpaddr2 xpaddr3 xpaddr4 xpaddr5 xpaddr6 xpaddr7 xpaddr8 xpaddr9 xpaddr10 xpaddr11 xpdata0 xpdata1 xpdata2 xpdata3 xpdata4 xpdata5 xpdata6 xpdata7 xpdata8 xpdata9 xpdata10 xpdata11 xpdata12 xpdata13 xpdata14 xpdata15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ba0 ba1 ldqm udqm xpaddr13 xpaddr14 xpdqm0 xpdqm1 xpcke xpsclk scke sclk xpcsn0 xprasn xpcasn xpwen nscs nsras nscas nwe figure 3-1. memory interface with 16-bit sdram (4mx16, 4banks) xpaddr0 xpaddr1 xpaddr2 xpaddr3 xpaddr4 xpaddr5 xpaddr6 xpaddr7 xpaddr8 xpaddr9 xpaddr10 xpaddr11 xpdata0 xpdata1 xpdata2 xpdata3 xpdata4 xpdata5 xpdata6 xpdata7 xpdata8 xpdata9 xpdata10 xpdata11 xpdata12 xpdata13 xpdata14 xpdata15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ba0 ba1 ldqm udqm xpaddr13 xpaddr14 xpdqm0 xpdqm1 xpcke xpsclk scke sclk xpcsn0 xprasn xpcasn xpwen nscs nsras nscas nwe xpaddr0 xpaddr1 xpaddr2 xpaddr3 xpaddr4 xpaddr5 xpaddr6 xpaddr7 xpaddr8 xpaddr9 xpaddr10 xpaddr11 xpdata16 xpdata17 xpdata18 xpdata19 xpdata20 xpdata21 xpdata22 xpdata23 xpdata24 xpdata25 xpdata26 xpdata27 xpdata28 xpdata29 xpdata30 xpdata31 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 ba0 ba1 ldqm udqm xpaddr13 xpaddr14 xpdqm2 xpdqm3 xpcke xpsclk scke sclk xpcsn0 xprasn xpcasn xpwen nscs nsras nscas nwe figure 3-2. memory interface with 16 -bit sdram (4mx16 * 2ea, 4banks)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdram controller 3 -5 addr ba data (cl2) data (cl3) sclk scke nscs ncas a10/ap nras nwe dqm ra trcd ra ba ca da db dc dd da db dc dd ba row active(a bank) read (a bank) (cl = 2 or cl = 3, bl = 4) ba bank a precharge rb bb cb bb da db dc dd rb trc row active(b bank) write (b bank) trp da db dc dd figure 3-3. sdram timing diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdram controller s3c24 a0 risc microprocessor 3-6 sdram configuration register register address r/w description reset value sdram_bankcfg 0x40c40000 r/w port 1 sdram configuration register 0x9f0c sdram_bankcfg bit description initial state ds [30:29] driver strength control 00 = full 01 = half 10 = weak 11 = rfu note : ds bit fields are only for mobile sdram. 00 b tcsr [28:27] temperature compensated self refresh control 00 = 46 ~ 70 o c 01 = 16 ~ 45 o c 10 = -25 ~ 15 o c 11 = 71 ~ 85 o c note: tcsr bit fields are only for mobile sdram. 00b pasr [26:24] partial array self refresh control 000 = 4banks 001 = 2banks 010 = 1banks 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved note: pasr bit fields are only for mobile sdram. 00b reserved [23:21] reserved pwrdn [20] 0 : not support sdram power down control 1 : support sdram power down control 0 tras [19:16] row active time 0000 = 1-clock 0001 = 2-cloc k 0010 = 3-clock 0011 = 4- clock 0100 = 5-clock 0101 = 6-cloc k 0110 = 7-clock 0111 = 8- clock 1000 = 9-clock 1001 = 10-clo ck 1010 = 11-clock 1011 = 12- clock 1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16- clock 1001b trc [15:12] row cycle time 0000 = 1-clock 0001 = 2-cloc k 0010 = 3-clock 0011 = 4- clock 0100 = 5-clock 0101 = 6-cloc k 0110 = 7-clock 0111 = 8- clock 1000 = 9-clock 1001 = 10-clock 1010 = 11-clock 1011 = 12- clock 1100 = 13-clock 1101 = 14-clock 1110 = 15-clock 1111 = 16- clock 1001b trcd [11:10] ras to cas delay 00 = 1-clock 01 = 2-clock 10 = 3-clock 11 = 4-clock 11b
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdram controller 3 -7 trp [9:8] row pre-charge time 00 = 1-clock 01 = 2-clock 10 = 3-clock 11 = 4-clock 11b density1 [7:6] sdram base component density of bank 1 00 = 16mbit 01 = 64mbit 10 = 128mbit 11 = 256mbit and 512mbit 00b density0 [5:4] sdram base component density of bank 0 00 = 16mbit 01 = 64mbit 10 = 128mbit 11 = 256mbit and 512mbit 00b cl [3:2] cas latency 00 = reserved 01 = 1-clock 10 = 2-clock 11 = 3-clock 11b ap [1] auto pre-charge control 0 = enable auto pre-charge 1 = disable auto pre-charge 10b dw [0] determine data bus width 0 = 32-bit 1 = 16-bit 00b note: sdram_bankcfg register should not be written when the sdra m controller is busy. the controller status bit, busy in sdram_bankcon register, can be used to check if the controller is idle. sdram control register register address r/w description reset value sdram_bankcon 0x40c40004 r/w port 1 sdram control register 0x00 sdram_bankcon bit description initial state reserved [31:4] reserved 0b busy [3] sdram controller status bit (read only) 0 = idle 1 = busy 0b wbuf [2] write buffer control 0 = disable 1 = enable n ote: write buffer mentioned above is in sdram controller. if write buffer is disabled, data is written to the external sdram memory immediately. if write buffer is enabled, data is flushed to the external sdram memory when write buffer is full. 0b init [1:0] sdram initialization control 00 = normal operation 01 = issue pall command 10 = issue mrs command 11 = issue emrs command note: emrs command is only for mobile sdram. 00b refresh control register register address r/w description reset value sdram_refresh 0x40c40008 r/w sdram refresh control register 0x0020
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdram controller s3c24 a0 risc microprocessor 3-8 sdram_refresh bit description initial state refcyc [15:0] sdram refresh cycle. example: refresh period is 15.6us, and hclk is 66mhz. the value of refcyc is as follows: refcyc = 15.6 x 10 -6 x 66 x 10 6 = 1029 100000b notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -1 nand flash controller (preliminary) overview recently, a nor flash memory gets high in price while an sdram and a nand flash memory get moderate, motivating some users to execute the boot code on a nand flash and execute the main code on an sdram. S3C24A0 boot code can be executed on an external nand flash memory. in order to support nand flash boot loader, the S3C24A0 is equipped with an internal sram buffer called ?steppingstone?. when booting, the first 4 kbytes of the nand flash memory will be loaded into steppingstone and the boot code loaded into steppingstone will be executed. generally, the boot code will copy na nd flash content to sdram. using hardware ecc, the nand flash data validity will be checked. upon the completion of the copy, the main program will be executed on the sdram. features ? support up to 2gbit nand flash memory. ? support 256/512/1k/2k byte page, 3,4 or 5 address cycle nand flash memory ? auto boot mode : the boot code is transferred into steppingstone during reset. after the transfer, the boot code will be executed on the steppingstone. ? auto load mode : support automatically one or more page load from flash memory to steppingstone ? auto store mode : support automatically one page store to flash memory from steppingstone ? software mode : user can directly access nand flash memory, for example this feature can be used in read/erase/program nand flash memory ? memory bus interface : 8 / 16-bit nand flash memory interface bus ? hardware ecc generation, detection and indication (software correction) ? sfr i/f : support little endian mode, byte/half word/word access ? steppingstone i/f : support little endian, byte/half word/word access ? the steppingstone 4-kb internal sram buffer can be used for another purpose after nand flash booting
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-2 pin configuration here is a configuration of nand flash controller of S3C24A0. users can select configuration of nand flash memory according to the table below. there is some differences between conventional nand flash memory and new advance flash memory. so users have to select the configuration properly. advance flash page size bus width real page size organization 0 256byte - 0 1 256word 16bitx1 0 512byte 8bitx1 0 1 1 1kbyte 8bitx2 0 1kbyte - 0 11kword 16bitx1 0 2kbyte 8bitx1 1 1 1 4kbyte 8bitx2 advance flash address cycle real cycle 0 3cycle(256m) 0 1 4cycle(512m) 0 4cycle(1g) 1 1 5cycle(2g) table 4-1 advance nand flash controller configuration (word means 16-bit in this table)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -3 block diagram sfr ecc gen. steppingstone (sram : 4kb) steppingstone controller system bus nand flash interface cle ale nce nre nwe r/nb0 i/o0~i/o15 r/nb1 ahb slave i/f control & state machine figure 4-1 nand flash controller block diagram boot loader function when power-on or system reset is occurred, the nand flash controller loads automatically the 4-kbytes boot loader codes. after loading the boot loader codes, the boot loader code is executed on the steppingstone. steppingstone (4 kb buffer) nand flash controller nand flash memory special function registers auto boot core access (boot code) user access figure 4-2 nand flash controller boot loader block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-4 operation mode steppingstone (4 kb buffer) nand flash controller nand flash memory special function registers auto load/store mode s/w mode core access user access figure 4-3 nand flash controller operation mode block diagram figure 4-3 describes all operation modes of the nand flash controller. the nand flash controller controls the auto load and store page(s) by using the steppingstone aut omatically in auto load or store mode. in software mode, you can access the nand flash memory directly using the command, address and data register. hclk flash_cle flash_nwe tacls twrph0 twrph1 flash_i/o command flash_ale address tacls twrph0 twrph1 figure 4-4 auto mode timing diagram (tacls = 1, twrph0 = 0, twrph1 = 0)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -5 auto load mode auto load function supports automatically load the page(s) of the nand flash memory to steppingstone up to 4kbytes. you can specify the load start address of the steppingstone and how many pages are loaded. auto load programming guide 1) set command (read command), address (of the page you read), and configuration and control value. 2) set the mode bit of the controller register to 0b01(auto load start) 3) once you set the mode bit to auto mode, the nand flash controller automatically load the page(s) you specify from the nand flash memory. 4) when auto loading is completed, the mode is rese t to 0b00 and the loaddone bit of the status register is set. also you can know this event by using auto load done interrupt note : the nand flash controller only load main area data (256 or 512 bytes), not the spare area data. so you need to access the spare area, you have to use the software mode (refer to the software mode). hclk flash_nre twrph0 twrph1 flash_i/o 1st data 2nd data n-1th data nth data twrph0 twrph0 twrph1 twrph0 twrph1 flash_rnb figure 4-5 nand flash controller auto load timing diagram (twrph0 = 0, twrph1 = 0) auto store mode auto store function supports automatically store a page from the steppingstone to the nand flash memory. you can specify the store start address of the steppingst one. in auto store mode, only one page store is supported. auto store programming guide 1) set command (1 st program command), address (of the page you store), configuration and control value. 2) set mode bit of the controller register to 0b10(auto store start) 3) once you set mode bit to the auto store mode, the nand flash controller automatically store a page to the nand flash memory.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-6 4) when auto storing is completed, the mode is rese t to 0b00 and the storedone bit of the status register is set. also you can know this event by using auto store done interrupt note : the nand flash controller only store main area dat a (256 or 512 bytes), not the spare area data. so you need to access the spare area, you have to use the software mode (refer to the software mode). hclk flash_nwe twrph0 twrph1 flash_i/o twrph0 twrph0 twrph1 twrph0 twrph1 flash_rnb 1st data 2nd data n-1th data nth data figure 4-6 nand flash controller auto store timing diagram (twrph0 =0, twrph1 = 0) software mode in the software mode, you can fully access the nand flash controller. the nand flash controller supports direct access interface with the nand flash controller. 1) the writing to the command register = the nand flash memory command cycle 2) the writing to the address register = the nand flash memory the address cycle 3) the writing to the data register = write data to the nand flash memory (write cycle) 4) the reading from the data register = r ead data from the nand flash memory (read cycle) 5) the reading main ecc registers and spare ecc registers = read data from the nand flash memory note : in the software mode, you have check the flash_rnb status input pin by using polling or interrupt.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -7 stepping stone (4k-byte sram) the nand flash controller uses steppingstone as the buffer in the auto load and store mode. also you can use this area for another purpose, if you don?t use auto load and store function. for the best performance, if you need to move the content of the nand flash memory to sdram, we recommend that you use dma burst transfer(source address : steppingstone, destination address : sdram). the nand flash controller supports that the nand flash controller and other masters can access the steppingstone concurrently. for example, 1k-byte of the steppingstone area have valid data, and the nand flash controller is moving data from the nand flash memory to steppingstone(area : 1k ~ 4k-byte). you can move 0 ~ 1k-byte data to the other memory area using dma burst transfer(dma burst tranfer is the best solution for the high speed). error correction code nand flash controller has four ecc (error correction code) modules. the two ecc modules (one for data[7:0] and the other for data[15:8]) can be used for (up to) 2048 bytes ecc parity code generation, and the others(one for data[7:0] and the other for data[15:8]) can be used for (up to) 16 bytes ecc parity code generation. 28bit ecc parity code = 22bit line parity + 6bit column parity 14bit ecc parity code = 8bit line parity + 6bit column parity data7 data6 data5 data4 data3 data2 data1 data0 ecc0 p64 p64? p32 p32? p16 p16? p8 p8? ecc1 p1024 p1024? p512 p512? p256 p256? p128 p128? ecc2 p4 p4? p2 p2? p1 p1? p2048 p2048? ecc3 p8192 p8192? p4096 p4096? 0 0 0 0 table 4-2 2k byte main area ecc parity code assignment table data7 data6 data5 data4 data3 data2 data1 data0 ecc0 p16 p16? p8 p8? p4 p4? p2 p2? ecc1 p1 p1? p64 p64? p32 p32? 0 0 table 4-3 16 byte spare area ecc parity code assignment table ecc module features 1) in auto load & auto store mode, ecc module generates automatically ecc parity code. 2) in software mode, ecc generation is controlled by the ecc lock (mainecclock, spareecclock) bit of the control register. ecc programming guide 1) in auto store mode in auto store mode, ecc module generates automatically ecc parity code for main data(256 or 512
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-8 bytes), not for spare area data. after auto store is completed, you may need to recode the ecc parity code generated to the spare area of nand flash memory. in this case, you just do read the first, second and third ecc status registers and writes to the spare area. 2) in auto load mode in auto load mode, ecc module also generates automatically ecc parity code for main data. after auto load is completed, you may need to check that the content of nand flash memory have no bit error. in this case, you just do read the first, second and third ecc value from the spare area through the main data area ecc0, ecc1 and ecc2 register. 3) in software mode a. in software mode, ecc module generates ecc parity code for all read / write data. so you have to reset ecc value before read or write data using t he initecc bit of the control register and have to set the mainecclock bit of the control register to ?0?. mainecclock and spareecclock bit control whether ecc parity code is generated or not. b. after you reset ecc parity code. whenever y ou read or write data, the ecc module generate ecc parity code on this data. c. after you finished read or write all page data. set the mainecclock bit to ?1?. ecc parity code is locked and the value of the ecc status register isn?t changed. from now as described in auto store & load mode, you can use these values to record to the spare area or check the bit error. nand flash memory configurations figure 4-7 ~ figure 4-9 discribe the configuration of nand flash memory. if you use nand flash memory as a boot memroy, you can use one of the these memory configruration. but if you use nand flash memory as a i/o memory not a boot memory, you have to connect ngcs[0] si gnal to boot rom memory. in these case you can use nf_rnb[1] signal which is used as a selection signal of nand flash memory. also the nf_rnb[1] is internally fixed ?h?. i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 r/ b we ale cle ce re rnb0 nfwe ale cle nfce nfre data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] figure 4-7 8-bit nand flash memory interface
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -9 i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 r/ b we ale cle ce re rnb0 nfwe ale cle nfce nfre data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 r/ b we ale cle ce re data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] rnb1 nfwe ale cle nfce nfre figure 4-8 two 8-bit nand flash memory interface i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 r/ b we ale cle ce re i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 rnb0 nfwe ale cle nfce nfre data[7] data[6] data[5] data[4] data[3] data[2] data[1] data[0] data[15] data[14] data[13] data[12] data[11] data[10] data[9] data[8] figure 4-9 16-bit nand flash memory interface
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-10 nand flash controller special registers configuration register register address r/w description reset value nfconf 0x40c00000 r/w nand flash configuration register 0x00xf100x nfconf bit description initial state reserved [23] reserved 00 advance flash [22] supports 1g & 2g advance flash memory this bit indicates whether external memory is new version or not h/w set tceh [21:16] nce high hold time to break the sequential read cycle used only boot loader & auto load function duration = hclk * (tceh+1) 0x3f reserved [15] reserved 0 tacls [14:12] cle & ale duration setting value (0~7) duration = hclk * tacls 001 reserved [11] reserved 0 twrph0 [10:8] twrph0 duration setting value (0~7) duration = hclk * ( twrph0+1 ) 110 x16 device [7] 0 : external flash memories are not x16 device 1 : external flash memory is x16 device (read only) 0 twrph1 [6:4] twrph1 duration setting value (0~7) duration = hclk * ( twrph1+1 ) 110 hardware nce [3] hardware flash_nce control 0 : do not supports flash_nce control(manual set) 1 : supports flash_nce control 1 bus width [2] nand flash memory i/o bus width 0 : 8-bit bus (rnb0) 1 : 16-bit bus(rnb0 and rnb1) h/w set page size [1] auto load page size of nand flash memory 0 : 256/1k bytes, 1 : 512/2k bytes, h/w set address cycle [0] address cycle of nand flash memory 0 : 3/4 address cycle 1 : 4/5 address cycle h/w set
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -11 control register register address r/w description reset value nfcont 0x40c00004 r/w nand flash control register 0x0384 nfcont bit description initial state ldstraddr [27:16] the address of the steppingstone to read or write when auto loading or storing note: the bit [17:16] are fixed to zero. 0x00 enbillegalaccint [15] illegal access interrupt control 0 : disable interrupt 1 : enable interrupt 0 enbloadint [14] in auto load, data load completion interrupt control 0 : disable interrupt 1 : enable interrupt 0 enbstoreint [13] in auto store, data store completion interrupt control 0 : disable interrupt 1 : enable interrupt 0 enbrnbint [12] rnb status input signal transition interrupt control 0 : disable rnb interrupt 1 : enable rnb interrupt 0 rnb_transmode [11] rnb transition detection configuration 0 : detect low to high 1 : detect high to low 0 spareecclock [10] lock spare area ecc generation 0 : unlock 1 : lock 1 mainecclock [9] lock main data area ecc generation 0 : unlock 1 : lock 1 initecc [8] initialize ecc decoder/encoder(write-only) 0 : 1 : initialize ecc decoder/encoder 0 reg_nce [7] nand flash memory flash_nce control 0 : nand flash chip enable(active low) 1 : nand flash chip disable (after auto load / store, nce will be inactive) note: it is controlled automatically in auto load / store mode. you must control this value in software mode. but if hw_nce is set to 1, also controlled by h/w. 1 loadpagesize [6:4] auto load page size configuration (0 ~ 7) size = setting value + 1 000 lock-tight [3] lock-tight configuration 0: disable 1 : enable note: once you set this bit to 1, you can?t clear this. in this state, you can only read. 0 lock [2] lock configuration 0: disable 1: enable 1 mode [1:0] nand flash controller operating mode selection 00 = disable all mode 01 = auto load mode 10 = auto store mode 11 = software mode 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-12 command register register address r/w description reset value nfcmmd 0x40c00008 r/w nand flash command set register 0x00 nfcmmd bit description initial state nfcmmd1 [15:8] nand flash memory 2 nd command value - nfcmmd0 [7:0] nand flash memory command value 0x00 note : when you use advance flash memory, it has 2 nd cycle read command (h30). so if you want to do auto load you have to set the value at the reg_cmmd1. address register register address r/w description reset value nfaddr 0x40c0000c r/w nand flash address set register 0x0000xx00 nfaddr bit description initial state nfaddr3 [31:24] nand flash memory address value3 (this value is only used at 4 th or 5 th address cycle) 0x00 nfaddr 2 [23:16] nand flash memory address value2 0x00 nfaddr 1 [15:8] nand flash memory address value1 0xxx nfaddr 0 [7:0] nand flash memory address value0 in software mode, only this value is used for flash_io 0x00 note : advance flash?s 1 st and 2 nd address is always column address. it means you don?t need to care about 1 st and 2 nd address. so, when you want to do auto load or store, you can set the address from reg_addr1 to reg_addr2 for 4 cycle address memory and from reg_ addr1 to reg_addr3 for 5 cycle address memory. data register register address r/w description reset value nfdata 0x40c00010 r/w nand flash data register 0xxxxx nf_data bit description initial state nfdata1 [15:8] nand flash read/program data value for i/o[15:8] 0xxx nfdata0 [7:0] nand flash read/program data value for i/o[7:0] in case of write: programming data in case of read: reading data. these values are only used in software mode. 0xxx
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -13 main data area ecc0 register register address r/w description reset value nfmeccdata0 0x40c00014 r/w nand flash ecc register for main data read 0x00000000 nfmeccdata0 bit description initial state eccdata0_1 [15:8] 1 st ecc for i/o[15:8] 0x00 eccdata0_0 [7:0] 1 st ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 1 st ecc value from nand flash memory 0x00 main data area ecc1 register register address r/w description reset value nfmeccdata1 0x40c00018 r/w nand flash ecc register for main data read 0x00000000 nfmeccdata1 bit description initial state eccdata1_1 [15:8] 2 nd ecc for i/o[15:8] 0x00 eccdata1_0 [7:0] 2 nd ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 2 nd ecc value from nand flash memory 0x00 main data area ecc2 register register address r/w description reset value nfmeccdata2 0x40c0001c r/w nand flash ecc register for main data read 0x00000000 nfmeccdata2 bit description initial state eccdata2_1 [15:8] 3 rd ecc for i/o[15:8] 0x00 eccdata2_0 [7:0] 3 rd ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 3 rd ecc value from nand flash memory 0x00 main data area ecc3 register register address r/w description reset value nfmeccdata3 0x40c00020 r/w nand flash ecc register for main data read( advance flash memory have 4byte ecc code ) 0x00000000 nfmeccdata3 bit description initial state eccdata3_1 [15:8] 4 th ecc for i/o[15:8] 0x00 eccdata3_0 [7:0] 4 th ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 4 th ecc value from nand flash memory 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-14 spare area ecc0 register register address r/w description reset value nfseccdata0 0x40c00024 r/w nand flash ecc regi ster for spare area data read 0x00000000 nfseccdata0 bit description initial state spare eccdata0_1 [15:8] 1 st ecc for i/o[15:8] 0x00 spare eccdata0_0 [7:0] 1 st ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 1 st ecc value from nand flash memory 0x00 spare area ecc1 register register address r/w description reset value nfseccdata1 0x40000028 r/w nand flash ecc regi ster for spare area data read 0x00000000 nfseccdata1 bit description initial state spare eccdata1_1 [15:8] 2 nd ecc for i/o[15:8] 0x00 spare eccdata1_0 [7:0] 2 nd ecc for i/o[ 7:0] note : in software mode, read this register when you need to read 2 nd ecc value from nand flash memory 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -15 nf_conf status register register address r/w description reset value nfstat 0x40c0002c r/w nand flash operation status register 0xxx00 nfstat bit description initial state illegalaccess [16] once lock or lock-tight is enabled, the illegal access (program, erase ?) to the memory makes this bit set. to clear this value write ?1? 0 : illegal access is not detected 1 : illegal access is detected 0 autoloaddone [15] when auto load operation is completed, this value set and issue interrupt if enabled. to clear this value write ?1? 0 : auto load completion is not detected 1 : auto load completion is detected 0 autostoredone [14] when auto store operation is completed, this value set and issue interrupt if enabled. to clear this value write ?1? 0 : auto store completion is not detected 1 : auto store completion is detected 0 rnb_transdetect [13] when rnb transition is occurred, this value set and issue interrupt if enabled. to clear this value write ?1? 0 : rnb transition is not detected 1 : rnb transition is detected 0 flash_nce [12] the status of flash_nce output pin (read-only) 1 flash_rnb1 [11] the status of flash_rnb1 input pin (read-only) 0 : nand flash memory busy 1 : nand flash memory ready to operate x flash_rnb0 [10] the status of flash_rnb0 input pin (read-only) 0 : nand flash memory busy 1 : nand flash memory ready to operate x ston_a2 [9:0] steppingstone access address (read-only) this address indicates which part of the memory is accessed by the nand flash controller and is valid in auto load / store mode 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-16 ecc0 status register register address r/w description reset value nfestat0 0x40c00030 r/w nand flash ecc status register for i/o [7:0] 0x00000000 nfestat0 bit description initial state serrordatano [24:21] in spare area, indicates which number data is error 00 serrorbitno [20:18] in spare area, indicates which bit is error 000 merrordatano [17:7] in main data area, indicates which number data is error 0x00 merrorbitno [6:4] in main data area, indicates which bit is error 000 spareerror [3:2] indicates whether spare area bit fail error occurred 00 : no error 01 : 1-bit error(correctable) 10 : multiple error 11 : ecc area error 00 mainerror [1:0] indicates whether main data area bit fail error occurred 00 : no error 01 : 1-bit error(correctable) 10 : multiple error 11 : ecc area error 00 note : the above values are only valid when both nfmeccdatan(nfseccdatan) and nfmeccn(nfsecc) have valid value. ecc1 status register register address r/w description reset value nfestat1 0x40c00034 r/w nand flash ecc status register for i/o [15:8] 0x00000000 nfestat1 bit description initial state serrordatano [24:21] in spare area, indicates which number data is error 00 serrorbitno [20:18] in spare area, indicates which bit is error 000 merrordatano [17:7] in main data area, indicates which number data is error 0x00 merrorbitno [6:4] in main data area, indicates which bit is error 000 spareerror [3:2] indicates whether spare area bit fail error occurred 00 : no error 01 : 1-bit error(correctable) 10 : multiple error 11 : ecc area error 00 mainerror [1:0] indicates whether main data area bit fail error occurred 00 : no error 01 : 1-bit error(correctable) 10 : multiple error 11 : ecc area error 00 note : the above values are only valid when both nfmeccdatan(nfseccdatan) and nfmeccn(nfsecc) have valid value.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -17 main data area ecc0 status register register address r/w description reset value nfmecc0 0x40c00038 r nand flash ecc register for i/o [7:0] 0xxxxxxx nfmecc0 bit description initial state mecc0_3 [31:24] ecc: error correction code #3 0xxx mecc0_2 [23:16] ecc: error correction code #2 0xxx mecc0_1 [15:8] ecc: error correction code #1 0xxx mecc0_0 [7:0] ecc: error correction code #0 0xxx main data area ecc1 status register register address r/w description reset value nfmecc1 0x40c0003c r nand flash ecc register for data[15:8] 0xxxxxxx nfmecc1 bit description initial state mecc1_3 [31:24] ecc: error correction code #3 0xxx mecc1_2 [23:16] ecc: error correction code #2 0xxx mecc1_1 [15:8] ecc: error correction code #1 0xxx mecc1_0 [7:0] ecc: error correction code #0 0xxx spare area ecc status register register address r/w description reset value nfsecc 0x40c00040 r nand flash ecc register for i/o [15:0] 0xxxxxxx nfsecc bit description initial state secc1_1 [31:24] spare area ecc1 status for i/o[15:8] 0xxx secc1_0 [23:16] spare area ecc0 status for i/o[15:8] 0xxx secc0_1 [15:8] spare area ecc1 status for i/o[7:0] 0xxx secc0_0 [7:0] spare area ecc0 status for i/o[7:0] 0xxx
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. nand flash controller S3C24A0 risc microprocessor 4-18 start block address register register address r/w description reset value nfsblk 0x40c00044 r/w nand flash programmable start block address 0x000000 nfsblk bit description initial state sblk_addr2 [23:16] the 3 rd block address of the block erase operation 0x00 sblk_addr1 [15:8] the 2 nd block address of the block erase operation 0x00 sblk_addr0 [7:0] the 1 st block address of the block erase operation (only bit [7:5] are valid when external memory is old version and only bit [7:6] are valid when external memory is new version) 0x00 note : advance flash?s block address starts from 3 address cycle. so block address register only need 3byte . end block address register register address r/w description reset value nfeblk 0x40c00048 r/w nand flash programmable end block address 0x000000 nfeblk bit description initial state eblk_addr2 [23:16] the 3 rd block address of the block erase operation 0x00 eblk_addr1 [15:8] the 2 nd block address of the block erase operation 0x00 eblk_addr0 [7:0] the 1 st block address of the block erase operation (only bit [7:5] are valid when external memory is old version and only bit [7:6] are valid when external memory is new version) 0x00 note : advance flash?s block address starts from 3 addre ss cycle. so block address register only need 3byte .
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor nand flash controller 4 -19 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor bus matrix 5-1 bus matrix overview S3C24A0 matrix provides the inte rface between dual ahb bus and memory sub-system. it is used for achieving high system performance by accessi ng various kinds of memory (sdram, sram, flash memory, rom etc) from different ahb bus (one is for system and the other is fo r image) at the same time. S3C24A0 have two matrix cores because it has two memory ports, and each matrix can sele ct the priority between rotation type and fixed type. user can select which one is excell ent for improving system performance. figure 5-1 shows the configuration of matrix and memory sub-system of S3C24A0. it also shows the model of external memory. both ahb bus can access all matrix core and matrix core is dedicated each memory port respectively. so it can operate separately at t he same time. it?s a key of matrix. figure 5-1 configuration of matrix and memory sub-system srom/ nfcon srom srom sdram sdram sromc/ nflashc sdramc external memory interface matrix sfr matrix core1 ahb-s ahb-i external memory matrix core0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. bus matrix S3C24A0 risc microprocessor 5-2 special function registers sromc/nflashc arbiter priority register (priority0) register address r/w description reset value priority0 0x40ce0000 r/w prior ity control register 0x0000_0000 priority0 bit description initial state fix_pri_typ [1] priority type 0: provide higher priority to s-bus when user set fixed priority 1: provide higher priority to i-bus when user set fixed priority 0 pri_typ [0] priority type 0: fixed priority 1: rotating priority 0 sdramc arbiter priority register (priority1) register address r/w description reset value priority1 0x40ce0004 r/w priority control register 0x0000_0000 priority1 bit description initial state fix_pri_typ [1] priority type 0: provide higher priority to s-bus when user set fixed priority 1: provide higher priority to i-bus when user set fixed priority 0 pri_typ [0] priority type 0: fixed priority 1: rotating priority 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -1 interrupt controller overview the interrupt controller in S3C24A0 receives the reques ts for interrupt services from 61 interrupt sources. these interrupt sources are provided by internal peripher als such as a dma controller, uart and iic, etc. among these interrupt sources, the uart0 and uart1 error interr upts are 'or'ed to the interrupt controller. and, two interrupts from a display/post processor , two interrupts from timer3/timer4, and four interrupts from dma controller are individually ?or?ed to the interrupt controlle r. also, the irda/memory stick interrupts, two interrupts from adc/penup/pendn are individually ?or?ed to the interrupt controller. the role of the interrupt controller is to ask for the f iq or irq interrupt requests to the arm926ej core after the arbitration process when there are multiple interrupt requests from internal peripherals and external interrupt request pins. the arbitration process is performed by the hardware priori ty logic and the result is written to the interrupt pending register and users notice that register to know which interrupt has been requested. functional description f-bit and i-bit of psr (pr ogram status register) if the f-bit of psr (program status register in arm 926ej cpu) is set to 1, the cpu does not accept the fiq (fast interrupt request) from the interrupt controller. if i- bit of psr (program status register in arm926ej cpu) is set to 1, the cpu does not accept the irq (interrupt request) from the interrupt controller. so, to enable the interrupt reception, the f-bit or i-bit of psr has to be cleared to 0 and also the corresponding bit of intmsk has to be set to 0. interrupt mode arm926ej has 2 types of interrupt mode, fiq or irq. a ll the interrupt sources determine the mode of interrupt to be used at interrupt request.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-2 interrupt pending register S3C24A0 has two interrupt pending resisters. the one is source pending register(srcpnd), the other is interrupt pending register(intpnd). these pending register s indicate whether or not an interrupt request is pending. when the interrupt sources request interrupt serv ice the corresponding bits of srcpnd register are set to 1, at the same time the only one bit of intpnd register is set to 1 automatically after arbitration process. if interrupts are masked, the corresponding bits of srcpnd regi ster are set to 1, but the bit of intpnd register is not changed. when a pending bit of intpnd register is set, t he interrupt service routine starts whenever the i-flag or f-flag is cleared to 0. the srcpnd and intpnd register s can be read and written, so the service routine must clear the pending condition by writing a 1 to the corres ponding bit in srcpnd register first and then clear the pending condition in intpnd registers same method. interrupt mask register indicates that an interrupt has been disabled if the corre sponding mask bit is 1. if an interrupt mask bit of intmsk is 0, the interrupt will be serviced normally. if the corre sponding mask bit is 1 and the interrupt is generated, the source pending bit will be set.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -3 interrupt sources interrupt controller supports 61 interrupt sources as shown in below table. among the 32 interrupt sources, each interrupt s ource corresponding to int_adc, int_pcm_mstick, int_ac97_nflash, int_dma_pbus, int_dma_gbus , int_dma_mbus, int_uart0, int_uart1, and int_campro is an ?or?ed interrupt which combines multiple subinterrupt sources connected to the corresponding interrupt sources, and provides a si ngle interrupt source to interrupt controller. sources descriptions arbiter group int_adc_ penup_down adc eoc/pen up/pen down interrupt arb5 int_rtc rtc alarm interrupt arb5 int_vlx_spi1 spi1 interrupt arb5 int_irda_mstick irda/ mstick interrupt arb5 int_iic iic interrupt arb4 int_usbh usb host interrupt arb4 int_usbd usb device interrupt arb4 int_ac97_nflash ac97/nflash interrupt arb4 int_uart1 uart1 interrupt ( err,rxd,txd) arb4 int_spi0 spi0 interrupt arb4 int_sdi sdi interrupt arb3 int_dma dma channels for s-bus interrupt arb3 int_ modem modem interface interrupt arb3 int_camif_preview camera interface interrupt arb3 int_uart0 uart0 interrupt ( err,rxd,txd) arb3 int_wdt_batflt wdt/batflt interrupt arb3 int_camif_codec camera interface interrupt arb2 int_lcd_post lcd/post interrupt arb2 int_timer3,4 timer3/4 interrupt arb2 int_timer2 timer2 interrupt arb2 int_timer1 timer1 interrupt arb2 int_timer0 timer0 interrupt arb2 int_keypad keypad interrupt arb1 int_me me interrupt arb1 int_mc mc interrupt arb1 int_dctq dctq interrupt arb1 int_tic rtc time tick interrupt arb1 eint15_18 external interrupt 15-18 arb1 eint11_14 external interrupt 11-14 arb0 eint7_10 external interrupt 7-10 arb0 eint3_6 external interrupt 3-6 arb0 eint0_2 external interrupt 0-2 arb0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-4 interrupt priority generating block the priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in the following figure. figure 6-1. priority generating block arm irq arbiter6 arbiter0 req1/eint0_2 req2/eint3_6 req3/eint7_10 req4/eint11_14 arbiter1 req1/eint15_18 req2/int_tic req3/dctq req4/int_mc req5/int_me req6/int_keypad arbiter2 req1/int_timer0 req2/int_timer1 req3/int_timer2 req4/int_timer3,4 req5/int_lcd_post req6/int_camif_codec arbiter3 req1/int_wdt_batflt req2/int_uart0 req3/int_camif_preview req4/int_modem req5/int_dma req6/int_sdi arbiter4 req1/int_spi0 req2/int_uart1 req3/int_ac97_nflash req4/int_usbd req5/int_usbh req6/int_iic arbiter5 req1/int_irda_mstick req2/int_vlc_spi1 req3/int_rtc req4/int_adc_penup_pendn
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -5 interrupt priority each arbiter can handle six interrupt requests based on the one bit arbiter mode control(arb_mode) and two bits of selection control signals(arb_sel) as follows: if arb_sel bits are 00b, the priority order is req0, req1, req2, req3, req4, and req5. if arb_sel bits are 01b, the priority order is req0, req2, req3, req4, req1, and req5. if arb_sel bits are 10b, the priority order is req0, req3, req4, req1, req2, and req5. if arb_sel bits are 11b, the priority order is req0, req4, req1, req2, req3, and req5. note that req0 of an arbiter is always the highest prio rity, and req5 is the lowest one. in addition, by changing the arb_sel bits, we can rotate the priority of req1 - req4. here, if arb_mode bit is set to 0, arb_sel bits are not automatically changed, thus the arbiter operates in the fixed priority mode. (note that even in this mode, we can change the priority by manually changing the arb_sel bits.). on the other hand, if arb_mode bit is 1, arb_sel bits are changed in rotation fashion, e.g., if req1 is serviced, arb_sel bits are changed to 01b automatically so as to make req1 the lowest priority one. the detailed rule of arb_sel change is as follows. if req0 or req5 is serviced, arb_sel bits are not changed at all. if req1 is serviced, arb_sel bits are changed to 01b. if req2 is serviced, arb_sel bits are changed to 10b. if req3 is serviced, arb_sel bits are changed to 11b. if req4 is serviced, arb_sel bits are changed to 00b. vectored interrupt mode (only for irq) S3C24A0 has a vectored interrupt mode, to reduce the interrupt latency time. if arm926ej receives the irq interrupt request from the interrupt controller, it executes an instruction at 0x00000018. the ldr instruction which loads to pc the address written in vector address register, one of special function registers in interrupt c ontroller, is located at 0x00000018. that is, @0x0000_0018 : ldr pc, [var] where, var is the special function regi ster at 0x4020_002c of interrupt controller.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-6 the ldr instruction lets the program counter be the ve ctor table address corresponding to each interrupt source. the user program code must locate the branch instruct ion, which branches to the corresponding isr (interrupt service routine) at each vector table address. for example, if timer1 is irq, the ldr instructi on at 0x00000018 which lets pc be 0x0000004c, is executed . 0x0000004c is automatically written to vect or address register by hardware logic. and the branch instruction, which jump s to the isr, is located at 0x0000004c. vector number vector name interrupt vector address 0 eint0_2 0x0000_0020 1 eint3_6 0x0000_0024 2 eint7_10 0x0000_0028 3 eint11_14 0x0000_002c 4 eint15_18 0x0000_0030 5 int_tick 0x0000_0034 6 int_dctq 0x0000_0038 7 int_mc 0x0000_003c 8 int_me 0x0000_0040 9 int_keypad 0x0000_0044 10 int_timer0 0x0000_0048 11 int_timer1 0x0000_004c 12 int_timer2 0x0000_0050 13 int_timer3,4 0x0000_0054 14 int_lcd_post 0x0000_0058 15 int_camif_codec 0x0000_005c 16 int_wdt_batflt 0x0000_0060 17 int_uart0 0x0000_0064 18 int_camif_preview 0x0000_0068 19 int_modem 0x0000_006c 20 int_dma 0x0000_0070
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -7 21 int_sdi 0x0000_0074 22 int_spi0 0x0000_0078 23 int_uart1 0x0000_007c 24 int_ac97_nflash 0x0000_0080 25 int_usbd 0x0000_0084 26 int_usbh 0x0000_0088 27 int_iic 0x0000_008c 28 int_irda_mstick 0x0000_0090 29 int_vlx_spi1 0x0000_0094 30 int_rtc 0x0000_0098 31 int_adc_penup_down 0x0000_009c special function registers there are five control registers in the interrupt contro ller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register. all the interrupt requests from the interrupt sources are first registered in the source pending register. they are divided into two groups based on the interrupt mode register, i.e., one fiq request and the remaining irq requests. arbitration process is performed for the multiple irq requests based on the priority register. source pending register (srcpnd) srcpnd register is composed of 32 bits each of which is rela ted to an interrupt source. each bit is set to 1 if the corresponding interrupt source generates the interrupt request and waits for the interrupt to be serviced. by reading this register, we can see the interrupt sources wait ing for their requests to be serviced. note that each bit of srcpnd register is automatically set by the interr upt sources regardless of the masking bits in the intmask register. in addition, it is not affected by the priority logic of interrupt controller. in the interrupt service routine for a specific interrupt source, the corresponding bit of srcpnd register has to be cleared to get the interrupt request from the same source correctly. if you return from the isr without clearing the bit, interrupt controller operates as if another interrupt reques t comes in from the same source. in other words, if a specific bit of srcpnd register is set to 1, it is a lways considered as a valid interrupt request waiting to be serviced.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-8 the specific time to clear the corresponding bit depends on t he user's requirement. the bottom line is that if you want to receive another valid request from the same source you should clear the corresponding bit first, and then enable the interrupt. you can clear a specific bit of srcpnd register by writi ng a data to this register. it clears only the bit positions of srcpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are with no change. register address r/w description reset value srcpnd 0x40200000 r/w indicates the interrupt request status. 0 = the interrupt has not been requested 1 = the interrupt source has asserted the interrupt request 0x00000000 note : when the user clear a interrupt pending, specific bit of srcpnd and intpnd, has to clear the bit of srcpnd
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -9 srcpnd bit description initial state int_adc_penup_dow n [31] 0 = not requested, 1 = requested (subsrcpnd) 0 int_rtc [30] 0 = not requested, 1 = requested 0 int_vlx_spi1 [29] 0 = not requested, 1 = requested (subsrcpnd) 0 int_irda_mstick [28] 0 = not requested, 1 = requested (subsrcpnd) 0 int_iic [27] 0 = not requested, 1 = requested 0 int_usbh [26] 0 = not requested, 1 = requested 0 int_usbd [25] 0 = not requested, 1 = requested 0 int_ac97_nflash [24] 0 = not requested, 1 = requested (subsrcpnd) 0 int_uart1 [23] 0 = not requested, 1 = requested (subsrcpnd) 0 int_spi0 [22] 0 = not requested, 1 = requested 0 int_sdi [21] 0 = not requested, 1 = requested 0 int_dma [20] 0 = not requested, 1 = requested (subsrcpnd) 0 int_modem [19] 0 = not requested, 1 = requested 0 int_camif_preview [18] 0 = not requested, 1 = requested 0 int_uart0 [17] 0 = not requested, 1 = requested (subsrcpnd) 0 int_wdt_batflt [16] 0 = not requested, 1 = requested (subsrcpnd) 0 int_camif_codec [15] 0 = not requested, 1 = requested 0 int_lcd_post [14] 0 = not requested, 1 = requested (subsrcpnd) 0 int_timer3,4 [13] 0 = not requested, 1 = requested (subsrcpnd) 0 int_timer2 [12] 0 = not requested, 1 = requested 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-10 int_timer1 [11] 0 = not requested, 1 = requested 0 int_timer0 [10] 0 = not requested, 1 = requested 0 int_keypad [9] 0 = not requested, 1 = requested 0 int_me [8] 0 = not requested, 1 = requested 0 int_mc [7] 0 = not requested, 1 = requested 0 int_dctq [6] 0 = not requested, 1 = requested 0 int_tic [5] 0 = not requested, 1 = requested 0 eint15_18 [4] 0 = not requested, 1 = requested 0 eint11_14 [3] 0 = not requested, 1 = requested 0 eint7_10 [2] 0 = not requested, 1 = requested 0 eint3_6 [1] 0 = not requested, 1 = requested 0 eint0_2 [0] 0 = not requested, 1 = requested 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -11 interrupt mode register (intmod) this register is composed of 32 bits each of which is relat ed to an interrupt source. if a specific bit is set to 1, the corresponding interrupt is processed in the fiq (fast inte rrupt) mode. otherwise, it is processed in the irq mode (normal interrupt). note that at most only one interrupt source can be serv iced in the fiq mode in the interrupt controller. (you should use the fiq mode only for the urgent interrupt.) thus, only one bit of intmod can be set to 1 at most. this register is write-only one, thus it cannot be read out. register address r/w description reset value intmod 0x40200004 r/w interrupt mode regiseter. 0 = irq mode 1 = fiq mode 0x00000000 note : if an interrupt mode is set to fiq mode in intmod register, fiq interrupt will not affect intpnd and intoffset registers. the intpnd and intoffset regist ers are valid only for irq mode interrupt source. intmod bit description initial state int_adc_penup_down [31] 0 = irq, 1 = fiq 0 int_rtc [30] 0 = irq, 1 = fiq 0 int_vlx_spi1 [29] 0 = irq, 1 = fiq 0 int_irda_mstick [28] 0 = irq, 1 = fiq 0 int_iic [27] 0 = irq, 1 = fiq 0 int_usbh [26] 0 = irq, 1 = fiq 0 int_usbd [25] 0 = irq, 1 = fiq 0 int_ac97_nflash [24] 0 = irq, 1 = fiq 0 int_uart1 [23] 0 = irq, 1 = fiq 0 int_spi0 [22] 0 = irq, 1 = fiq 0 int_sdi [21] 0 = irq, 1 = fiq 0 int_dma [20] 0 = irq, 1 = fiq 0 int_modem [19] 0 = irq, 1 = fiq 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-12 int_camif_preview [18] 0 = irq, 1 = fiq 0 int_uart0 [17] 0 = irq, 1 = fiq 0 int_wdt_batflt [16] 0 = irq, 1 = fiq 0 int_camif_codec [15] 0 = irq, 1 = fiq 0 int_lcd_post [14] 0 = irq, 1 = fiq 0 int_timer3,4 [13] 0 = irq, 1 = fiq 0 int_timer2 [12] 0 = irq, 1 = fiq 0 int_timer1 [11] 0 = irq, 1 = fiq 0 int_timer0 [10] 0 = irq, 1 = fiq 0 int_keypad [9] 0 = irq, 1 = fiq 0 int_me [8] 0 = irq, 1 = fiq 0 int_mc [7] 0 = irq, 1 = fiq 0 int_dctq [6] 0 = irq, 1 = fiq 0 int_tic [5] 0 = irq, 1 = fiq 0 eint15_18 [4] 0 = irq, 1 = fiq 0 eint11_14 [3] 0 = irq, 1 = fiq 0 eint7_10 [2] 0 = irq, 1 = fiq 0 eint3_6 [1] 0 = irq, 1 = fiq 0 eint0_2 [0] 0 = irq, 1 = fiq 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -13 interrupt mask register (intmsk) each of the 32 bits in the interrupt mask register is relat ed to an interrupt source. if you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the cpu. (note that even in such a case, the corresponding bit of srcpnd register is set to 1). if the mask bit is 0, the interrupt request can be serviced. register address r/w description reset value intmsk 0x40200008 r/w determines which interrupt source is masked. the masked interrupt source will not be serviced. 0 = interrupt service is available 1 = interrupt service is masked 0xffffffff intmsk bit description initial state int_adc_penup_dow n [31] 0 = service available, 1 = masked 1 int_rtc [30] 0 = service available, 1 = masked 1 int_vlx_spi1 [29] 0 = service available, 1 = masked 1 int_irda_mstick [28] 0 = service available, 1 = masked 1 int_iic [27] 0 = service available, 1 = masked 1 int_usbh [26] 0 = service available, 1 = masked 1 int_usbd [25] 0 = service available, 1 = masked 1 int_ac97_nflash [24] 0 = service available, 1 = masked 1 int_uart1 [23] 0 = service available, 1 = masked 1 int_spi0 [22] 0 = service available, 1 = masked 1 int_sdi [21] 0 = service available, 1 = masked 1 int_dma [20] 0 = service available, 1 = masked 1 int_modem [19] 0 = service available, 1 = masked 1 int_camif_preview [18] 0 = service available, 1 = masked 1 int_uart0 [17] 0 = service available, 1 = masked 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-14 int_wdt_batflt [16] 0 = service available, 1 = masked 1 int_camif_codec [15] 0 = service available, 1 = masked 1 int_lcd_post [14] 0 = service available, 1 = masked 1 int_timer3,4 [13] 0 = service available, 1 = masked 1 int_timer2 [12] 0 = service available, 1 = masked 1 int_timer1 [11] 0 = service available, 1 = masked 1 int_timer0 [10] 0 = service available, 1 = masked 1 int_keypad [9] 0 = service available, 1 = masked 1 int_me [8] 0 = service available, 1 = masked 1 int_mc [7] 0 = service available, 1 = masked 1 int_dctq [6] 0 = service available, 1 = masked 1 int_tic [5] 0 = service available, 1 = masked 1 eint15_18 [4] 0 = service available, 1 = masked 1 eint11_14 [3] 0 = service available, 1 = masked 1 eint7_10 [2] 0 = service available, 1 = masked 1 eint3_6 [1] 0 = service available, 1 = masked 1 eint0_2 [0] 0 = service available, 1 = masked 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -15 priority register (priority) register address r/w description reset value priority 0x4020000c r/w irq priority control register 0x7f priority bit description initial state arb_sel6 [20:19] arbiter 6 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel5 [18:17] arbiter 5 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_sel4 [16:15] arbiter 4 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel3 [14:13] arbiter 3 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel2 [12:11] arbiter 2 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel1 [10:9] arbiter 1 group priority order set 00 = req 0-1-2-3-4-5 01 = req 0-2-3-4-1-5 10 = req 0-3-4-1-2-5 11 = req 0-4-1-2-3-5 0 arb_sel0 [8:7] arbiter 0 group priority order set 00 = req 1-2-3-4 01 = req 2-3-4-1 10 = req 3-4-1-2 11 = req 4-1-2-3 0 arb_mode6 [6] arbiter 6 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode5 [5] arbiter 5 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode4 [4] arbiter 4 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode3 [3] arbiter 3 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode2 [2] arbiter 2 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-16 arb_mode1 [1] arbiter 1 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1 arb_mode0 [0] arbiter 0 group priority rotate enable 0 = priority does not rotate, 1 = priority rotate enable 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -17 interrupt pending register (intipnd) each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request is the highest priority one that is unmasked and waits for the inte rrupt to be serviced. since intpnd is located after the priority logic, only one bit can be set to 1 at most, and t hat is the very interrupt request generating irq to cpu. in interrupt service routine for irq, you can read this regist er to determine the interrupt source to be serviced among 32 sources. like the srcpnd, this register has to be cleared in the interrupt service routine after clearing srcpnd register. we can clear a specific bit of intpnd register by writi ng a data to this register. it clears only the bit positions of intpnd corresponding to those set to one in the data. the bi t positions corresponding to those that are set to 0 in the data remains as they are with no change. register address r/w description reset value intpnd 0x40200010 r/w indicates the interrupt request status. 0 = the interrupt has not been requested 1 = the interrupt source has asserted the interrupt request 0x00000000 note : if the fiq mode interrupt is occurred, the corres ponding bit of intpnd will not be turned on. because the intpnd register is available only for irq mode interrupt. intpnd bit description initial state int_adc_penup_down [31] 0 = not requested, 1 = requested 0 int_rtc [30] 0 = not requested, 1 = requested 0 int_vlx_spi1 [29] 0 = not requested, 1 = requested 0 int_irda_mstick [28] 0 = not requested, 1 = requested 0 int_iic [27] 0 = not requested, 1 = requested 0 int_usbh [26] 0 = not requested, 1 = requested 0 int_usbd [25] 0 = not requested, 1 = requested 0 int_ac97_nflash [24] 0 = not requested, 1 = requested 0 int_uart1 [23] 0 = not requested, 1 = requested 0 int_spi0 [22] 0 = not requested, 1 = requested 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-18 int_sdi [21] 0 = not requested, 1 = requested 0 int_dma [20] 0 = not requested, 1 = requested 0 int_modem [19] 0 = not requested, 1 = requested 0 int_camif_preview [18] 0 = not requested, 1 = requested 0 int_uart0 [17] 0 = not requested, 1 = requested 0 int_wdt_batflt [16] 0 = not requested, 1 = requested 0 int_camif_codec [15] 0 = not requested, 1 = requested 0 int_lcd_post [14] 0 = not requested, 1 = requested 0 int_timer3,4 [13] 0 = not requested, 1 = requested 0 int_timer2 [12] 0 = not requested, 1 = requested 0 int_timer1 [11] 0 = not requested, 1 = requested 0 int_timer0 [10] 0 = not requested, 1 = requested 0 int_keypad [9] 0 = not requested, 1 = requested 0 int_me [8] 0 = not requested, 1 = requested 0 int_mc [7] 0 = not requested, 1 = requested 0 int_dctq [6] 0 = not requested, 1 = requested 0 int_tic [5] 0 = not requested, 1 = requested 0 eint15_18 [4] 0 = not requested, 1 = requested 0 eint11_14 [3] 0 = not requested, 1 = requested 0 eint7_10 [2] 0 = not requested, 1 = requested 0 eint3_6 [1] 0 = not requested, 1 = requested 0 eint0_2 [0] 0 = not requested, 1 = requested 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -19 interrupt offset register (intoffset) the number in the interrupt offset register shows which interrupt request of irq mode is in the intpnd register. this bit can be cleared automatically by clearing srcpnd and intpnd. register address r/w description reset value intoffset 0x40200014 r indicates the irq interrupt request source 0x00000000 int source the offset value int source the offset value int_adc_penup_down 31 int_camif_codec 15 int_rtc 30 int_lcd_post 14 int_vlx_spi1 29 int_timer3,4 13 int_irda_mstick 28 int_timer2 12 int_iic 27 int_timer1 11 int_usbh 26 int_timer0 10 int_usbd 25 int_keypad 9 int_ac97_nflash 24 int_me 8 int_uart1 23 int_mc 7 int_spi0 22 int_dctq 6 int_sdi 21 int_tic 5 int_dma 20 eint15_18 4 int_modem 19 eint11_14 3 int_camif_preview 18 eint7_10 2 int_uart0 17 eint3_6 1 int_wdt_batflt 16 eint0_2 0 note : if the fiq mode interrupt is occurred, the in toffset will not be affected. because the intoffset register is available only for irq mode interrupt.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-20 sub source pending register (subsrcpnd) you can clear a specific bit of subsrcpnd register by writing a data to this register. it clears only the bit positions of the subsrcpnd corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the dat a remains as they are with no change. register address r/w description reset value subsrcpnd 0x402000018 r/w indicates the interrupt request status. 0 = the interrupt has not been requested 1 = the interrupt source has asserted the interrupt request 0x00000000 subsrcpnd bit description initial state reserved [31:29] - - int_dma3 [28] 0 = not requested, 1 = requested 0 int_dma2 [27] 0 = not requested, 1 = requested 0 int_dma1 [26] 0 = not requested, 1 = requested 0 int_dma0 [25] 0 = not requested, 1 = requested 0 int_vlx [24] 0 = not requested, 1 = requested 0 int_spi1 [23] 0 = not requested, 1 = requested 0 int_ac97 [22] 0 = not requested, 1 = requested 0 int_nflash [21] 0 = not requested, 1 = requested 0 int_disp_frame [20] 0 = not requested, 1 = requested 0 int_adc [19] 0 = not requested, 1 = requested 0 int_pendn [18] 0 = not requested, 1 = requested 0 int_penup [17] 0 = not requested, 1 = requested 0 int_disp_fifo [16] 0 = not requested, 1 = requested 0 int_post [15] 0 = not requested, 1 = requested 0 int_batflt [14] 0 = not requested, 1 = requested 0 int_wdt [13] 0 = not requested, 1 = requested 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -21 int_timer4 [12] 0 = not requested, 1 = requested 0 int_timer3 [11] 0 = not requested, 1 = requested 0 reserved [10:8] - - int_mstick [7] 0 = not requested, 1 = requested 0 int_irda [6] 0 = not requested, 1 = requested 0 int_err1 [5] 0 = not requested, 1 = requested 0 int_txd1 [4] 0 = not requested, 1 = requested 0 int_rxd1 [3] 0 = not requested, 1 = requested 0 int_err0 [2] 0 = not requested, 1 = requested 0 int_txd0 [1] 0 = not requested, 1 = requested 0 int_rxd0 [0] 0 = not requested, 1 = requested 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-22 interrupt sub mask register (intsubmsk) each of the 32 bits in the interrupt mask register is relat ed to an interrupt source. if you set a specific bit to 1, the interrupt request from the corresponding interrupt source is not serviced by the cpu. (note that even in such a case, the corresponding bit of subsrcpnd register is set to 1). if the mask bit is 0, the interrupt request can be serviced. register address r/w description reset value intsubmsk 0x4020001c r/w determines which interrupt source is masked. the masked interrupt source will not be serviced. 0 = interrupt service is available 1 = interrupt service is masked 0x1fffffff intsubmsk bit description initial state reserved [31:29] - - int_dma3 [28] 0 = service available, 1 = masked 1 int_dma2 [27] 0 = service available, 1 = masked 1 int_dma1 [26] 0 = service available, 1 = masked 1 int_dma0 [25] 0 = service available, 1 = masked 1 int_vlx [24] 0 = service available, 1 = masked 1 int_spi1 [23] 0 = service available, 1 = masked 1 int_ac97 [22] 0 = service available, 1 = masked 1 int_nflash [21] 0 = service available, 1 = masked 1 int_disp_frame [20] 0 = service available, 1 = masked 1 int_adc [19] 0 = service available, 1 = masked 1 int_pendn [18] 0 = service available, 1 = masked 1 int_penup [17] 0 = service available, 1 = masked 1 int_disp_fifo [16] 0 = service available, 1 = masked 1 int_post [15] 0 = service available, 1 = masked 1 int_batflt [14] 0 = service available, 1 = masked 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor interrupt controller 6 -23 int_wdt [13] 0 = service available, 1 = masked 1 int_timer4 [12] 0 = service available, 1 = masked 1 int_timer3 [11] 0 = service available, 1 = masked 1 reserved [10:8] - - int_mstick [7] 0 = service available, 1 = masked - int_irda [6] 0 = service available, 1 = masked - int_err1 [5] 0 = service available, 1 = masked 1 int_txd1 [4] 0 = service available, 1 = masked 1 int_rxd1 [3] 0 = service available, 1 = masked 1 int_err0 [2] 0 = service available, 1 = masked 1 int_txd0 [1] 0 = service available, 1 = masked 1 int_rxd0 [0] 0 = service available, 1 = masked 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. interrupt controller S3C24A0 risc microprocessor 6-24 vectored interrupt mode register (vect_int_mode) this register is used to indicate if the vectored inte rrupt mode is enabled. if you set a bit[0] to 1, the vectored interrupt mode will be enabled. register address r/w description reset value vect_int_mode 0x40200020 r/w indicates if the vectored interrupt mode is enabled. 0 = nonvectored interrupt mode 1 = vectored interrupt mode 0x00000000 vect_int_mode bit description initial state reserved [31:1] - - vect_int_mode [0] 0 = vectored interrupt mode disable 1 = vectored interrupt mode enable 0 vector address register (var) this register is used to provide the interrupt vector address to which the program control branches. if irq occurs, the ldr instruction at 0x0000_0018 let pc be t he value written in this register. if vect_int_mode[0] is set to ?0?, the address in nonvect_addr is passed to this register, and if vect_int_mode[0] is set to ?1?, the address in vect_addr is passed to this register. register address r/w description reset value var 0x4020002c r provides the interrupt vector address - var bit description initial state var [31:0] provides the interrupt vector address -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-1 pwm timer(preliminary) overview the S3C24A0 has five 16-bit timers. the timer 0, 1, 2, 3 have pwm function(pulse width modulation). timer 4 has an internal timer only with no output pins. timer 0 has a dead-zone generator, which is used with a large current device. timer 0 and timer 1 share an 8-bit prescaler, timers 2, 3 and 4 share the other 8-bit prescaler. each timer has a clock-divider which has 4 different divided signals (1/2, 1/4, 1/8, 1/16). each timer block receives its own clock signals from the clock-divider, which receives the clock fr om the corresponding 8-bit prescaler. the 8-bit prescaler is programmable and divides the pclk according to t he loading value, which is stored in tcfg0 and tcfg1 registers. the timer count buffer register(tcntbn) has an initial va lue which is loaded into the down-counter when the timer is enabled. the timer compare buffer register(tcmpbn) has an initial value which is loaded into the compare register to be compared with the down-counter value. this double buffering feature of tcntbn and tcmpbn makes the timer generate a stable output when the frequency and duty ratio are changed. each timer has its own 16-bit down counter, which is dr iven by the timer clock. when the down counter reaches zero, the timer interrupt request is generated to info rm the cpu that the timer operation has been completed. when the timer counter reaches zero, the value of co rresponding tcntbn is automatically loaded into the down counter to continue the next operation. however, if the timer stops, for example, by clearing the timer enable bit of tconn during the timer running mode, the value of tcntbn will not be reloaded into the counter. the value of tcmpbn is used for pwm (pulse width modul ation). the timer control logic changes the output level when the down-counter value matches the value of the compar e register in the timer control logic. therefore, the compare register determines the turn-on time(or turn-off time) of an pwm output. feature ? five 16-bit timers ? two 8-bit prescalers & two 4-bit divider ? programmable duty control of output waveform (pwm) ? auto-reload mode or one-shot pulse mode ? dead-zone generator
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-2 clock divider 4:1 mux dead zone generator tout0 tout1 tout2 control logic0 tcmpb0 tcntb0 control logic1 tcmpb1 tcntb1 4:1 mux clock divider 4:1 mux 4:1 mux control logic2 tcmpb2 tcntb2 tout3 control logic3 tcmpb3 tcntb3 no pin pclk 8-bit prescaler 8-bit prescaler dead zone dead zone 1/8 1/4 1/16 1/2 1/8 1/4 1/16 1/2 4:1 mux control logic4 tcntb4 figure 7-1. 16-bit pwm timer block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-3 pwm timer operation prescaler & divider an 8-bit prescaler and 4-bit divider make the following output frequencies: 4-bit divider settings minimum resolution (prescaler = 0) maximum resolution (prescaler = 255) maximum interval (tcntbn = 65535) 1/2 ( pclk = 55 mhz ) 0.0363 us (27.5000 mhz ) 9.3090 us (107.4219 khz ) 0.6100 sec 1/4 ( pclk = 55 mhz ) 0.0727 us (13.7500 mhz ) 18.6181 us (53.7109 khz ) 1.2201 sec 1/8 ( pclk = 55 mhz ) 0.1454us ( 6.8750 mhz ) 37.2363 us (26.8554khz ) 2.4403 sec 1/16 ( pclk = 55 mhz ) 0.2909 us ( 3.4375mhz ) 74.4729 us (13.4277 khz ) 4.8806 sec basic timer operation 3 3 2 0 1 1 0 2 1 0 0 tcntbn=2 tcmpbn=0 manual update=0 auto-reload=1 interrupt request interrupt request tcntbn=3 tcmpbn=1 manual update=1 auto-reload=1 toutn tcmpn tcntn auto-reload=0 command status timer is started tcntn=tcmpn auto-reload start bit=1 tcntn=tcmpn timer is stopped. figure 7-2. timer operations a timer (except the timer ch-5) has tcntbn, tcnt n, tcmpbn and tcmpn. tcntbn and tcmpbn are loaded into tcntn and tcmpn when the timer reaches 0. when t cntn reaches 0, the interrupt request will occur if the interrupt is enabled. (tcntn and tcmpn are the names of t he internal registers. the tcntn register can be read from the tcnton register)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-4 auto-reload & double buffering S3C24A0 pwm timers have a double buffering feature, which can change the reload value for the next timer operation without stopping the current ti mer operation. so, although the new timer value is set, a current timer operation is completed successfully. the timer value can be written into tcntbn (timer count buffer register) and the current counter value of the timer can be read from tcnton (timer count observation r egister). if tcntbn is read, the read value is not the current state of the counter but the reload value for the next timer duration. the auto-reload is the operation, which copies the t cntbn into tcntn when tcntn reaches 0. the value, written into tcntbn, is loaded to tcntn only when t he tcntn reaches to 0 and auto-reload is enabled. if the tcntn is 0 and the auto-reload bit is 0, the tcntn does not operate any further. write tcntbn = 100 write tcntbn = 200 start tcntbn = 150 auto-reload 150 100 100 200 interrupt figure 7-3. example of double buffering feature
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-5 timer initialization using manua l update bit and inverter bit because an auto-reload operation of the timer occurs when t he down counter reaches to 0, a starting value of the tcntn has to be defined by the user at first. in this case, the starting value has to be loaded by the manual update bit. the sequence of starting a timer is as follows; 1) write the initial value into tcntbn and tcmpbn 2) set the manual update bit of the corresponding timer. it is recommended to configure the inverter on/off bit. (whether use inverter or not) 3) set start bit of corresponding timer to start the timer(at the same time, clear the manual update bit). also, if the timer is stopped by force, the tcntn reta ins the counter value and is not reloaded from tcntbn. if new value has to be set, manual update has to be done. note whenever tout inverter on/off bit is changed, the toutn logic value will be changed whether or not the timer runs. therefore, it is desirable that the inve rter on/off bit is configured with the manual update bit.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-6 example of a timer operation toutn 12 46 50 110 40 40 60 20 3 79 10 5 8 11 figure 7-4. example of a timer operation the result of the following procedure is shown in figure21-4; 1. enable the auto-reload feature. set the tcntbn as 160 (50+110) and the tcmpbn as 110. set the manual update bit and configure the inverter bit(on/off). the manual update bit sets tcntn and tcmpn to the values of tcntbn and tcmpbn, respectively. and then, set tcntbn and tcmpbn as 80 (40+40) and 40, respectively, to determine the next reload value. 2. set the start bit, provided that manual_update is 0 and in verter is off and auto-reload is on. the timer starts counting down after latency time within the timer resolution. 3. when tcntn has the same value with tcmpn, the logic level of toutn is changed from low to high. 4. when tcntn reaches 0, the interrupt request is gene rated and tcntbn value is loaded into a temporary register. at the next timer tick, tcntn is re loaded with the temporary register value(tcntbn). 5. in the isr(interrupt service routine), the tcntbn and tcmpbn are set as 80 (20+60) and 60, respectively, which is used for the next duration. 6. when tcntn has the same value as tcmpn, the lo gic level of toutn is changed from low to high. 7. when tcntn reaches 0, tcntn is reloaded automatically with tcntbn. at the same time, the interrupt request is generated. 8. in the isr (interrupt service routine), auto-rel oad and interrupt request are disabled to stop the timer. 9. when the value of tcntn is same as tcmpn, t he logic level of toutn is changed from low to high. 10. even when tcntn reaches to 0, tcntn is not any more reloaded and the timer is stopped because auto- reload has been disabled. 11. no interrupt request is generated.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-7 pwm (pulse width modulation) write tcmpbn = 60 write tcmpbn = 50 write tcmpbn = 40 write tcmpbn = 30 write tcmpbn = 30 write tcmpbn = next pwm value 60 50 40 30 30 figure 7-5. example of pwm pwm feature can be implemented by using the tcm pbn. pwm frequency is determined by tcntbn. a pwm value is determined by tcmpbn in figure 7-5. for a higher pwm value, decrease the tcmpbn value. fo r a lower pwm value, increase the tcmpbn value. if an output inverter is enabled, the in crement/decrement may be reversed. because of the double buffering feature, tcmpbn, for a next pwm cycle, can be written at any point in the current pwm cycle by isr or something else
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-8 output level control inverter off initial state period 1 period 2 timer stop inverter on figure 7-6. inverter on/off the following methods can be used to maintain tout as high or low.(assume the inverter is off) 1. turn off the auto-reload bit. and then, toutn goes to high level and the timer is stopped after tcntn reaches to 0. this method is recommended. 2. stop the timer by clearing the timer start/stop bit to 0. if tcntn tcmpn, the output level is high . if tcntn >tcmpn, the output level is low . 3. toutn can be inverted by the inverter on/off bit in tcon. the inverter removes the additional circuit to adjust the output level.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-9 dead zone generator the dead zone is for the pwm control in a power device. this feature is used to insert the time gap between a turn-off of a switching device and a turn on of another swit ching device. this time gap prohibits the two switching devices turning on simultaneously, even for a very short time. tout0 is the pwm output. ntout0 is the inversion of the tout0. if the dead zone is enabled, the output wave form of tout0 and ntout0 will be tout0_dz and ntout0_d z, respectively. ntout0_dz is routed to the tout1 pin. in the dead zone interval, tout0_dz and ntout0_dz can never be turned on simultaneously. tout0 ntout0 tout0_dz ntout0_dz deadzone interval figure 7-7. the wave form when a dead zone feature is enabled
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-10 dma request mode the pwm timer can generate a dma request at every specific times. the timer keeps dma request signal (ndma_req) low until the timer receives the ack signal. when the timer receives the ack signal, it makes the request signal inactive. the timer, which generates the dma request, is determined by setting dma mode bits(in tcfg1 register). if one of timers is configured as dma request mode, that timer does not generate an interrupt request. the others can generate interrupt normally. dma mode configuration and dma / interrupt operation dma mode dma request timer0 int timer1 int timer2 int timer3 int timer4 int 0000 no select on on on on on 0001 timer0 off on on on on 0010 timer1 on off on on on 0011 timer2 on on off on on 0100 timer3 on on on off on 0101 timer4 on on on on off 0110 no select on on on on on pclk int4tmp dmareq_en ndma_ack ndma_req int4 1 0 1 figure 7-8. the timer4 dma mode operation
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-11 pwm timer control registers timer configuration register0 (tcfg0) timer input clock frequency = pclk / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divider value} = 2, 4, 8, 16 register address r/w description reset value tcfg0 0x44000000 r/w configures the two 8-bit prescalers 0x00000000 tcfg0 bit description initial state reserved [31:24] 0x00 dead zone length [23:16] these 8 bits dete rmine the dead zone length. the 1 unit time of the dead zone length is equal to the 1 unit time of timer 0. 0x00 prescaler 1 [15:8] these 8 bits determine prescaler value for timer 2, 3 and 4 0x00 prescaler 0 [7:0] these 8 bits determine prescaler value for timer 0 and 1 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-12 timer configuration register1 (tcfg1) register address r/w description reset value tcfg1 0x44000004 r/w 5-mux & dma mode selecton register 0x00000000 tcfg1 bit description initial state reserved [31:24] 00000000 dma mode [23:20] select dma request channel 0000 = no select(all interrupt) 0001 = timer0 0010 = timer1 0011 = timer2 0100 = timer3 0101 = timer4 0110 = reserved 0000 mux 4 [19:16] select mux input for pwm timer4. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 0000 mux 3 [15:12] select mux input for pwm timer3. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 0000 mux 2 [11:8] select mux input for pwm timer2. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 0000 mux 1 [7:4] select mux input for pwm timer1. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 0000 mux 0 [3:0] select mux input for pwm timer0. 0000 = 1/2 0001 = 1/4 0010 = 1/8 0011 = 1/16 0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-13 timer control register (tcon) register address r/w description reset value tcon 0x44000008 r/w timer control register 0x00000000 tcon bit description initial state timer 4 auto reload on/off [22] this bit determines auto reload on/off for timer 4. 0 = one-shot 1 = interval mode (auto reload) 0 timer 4 manual update (note) [21] this bit determines the manual update for timer 4. 0 = no operation 1 = update tcntb4 0 timer 4 start/stop [20] this bit determines start/stop for timer 4. 0 = stop 1 = start for timer 4 0 timer 3 auto reload on/off [19] this bit determines auto reload on/off for timer 3. 0 = one-shot 1 = interval mode (auto reload) 0 timer 3 output inverter on/off [18] this bit det ermines output inverter on/off for timer 3. 0 = inverter off 1 = inverter on for tout3 0 timer 3 manual update (note) [17] this bit determine manual update for timer 3. 0 = no operation 1 = update tcntb3, tcmpb3 0 timer 3 start/stop [16] this bit determines start/stop for timer 3. 0 = stop 1 = start for timer 3 0 timer 2 auto reload on/off [15] this bit determines auto reload on/off for timer 2. 0 = one-shot 1 = interval mode (auto reload) 0 timer 2 output inverter on/off [14] this bit det ermines output inverter on/off for timer 2. 0 = inverter off 1 = inverter on for tout2 0 timer 2 manual update (note) [13] this bit determines the manual update for timer 2. 0 = no operation 1 = update tcntb2, tcmpb2 0 timer 2 start/stop [12] this bit determines start/stop for timer 2. 0 = stop 1 = start for timer 2 0 timer 1 auto reload on/off [11] this bit determines the auto reload on/off for timer1. 0 = one-shot 1 = interval mode (auto reload) 0 timer 1 output inverter on/off [10] this bit dete rmines the output inverter on/off for timer1. 0 = inverter off 1 = inverter on for tout1 0 timer 1 manual update (note) [9] this bit determines the manual update for timer 1. 0 = no operation 1 = update tcntb1, tcmpb1 0 timer 1 start/stop [8] this bit determines start/stop for timer 1. 0 = stop 1 = start for timer 1 0 reserved [7:5] - - note: this bit has to be cleared at next writing.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-14 tcon(continued) tcon bit description initial state dead zone enable [4] this bit determines the dead zone operation. 0 = disable 1 = enable 0 timer 0 auto reload on/off [3] this bit determines auto reload on/off for timer 0. 0 = one-shot 1 = interval mode(auto reload) 0 timer 0 output inverter on/off [2] this bit dete rmines the output inverter on/off for timer 0. 0 = inverter off 1 = inverter on for tout0 0 timer 0 manual update (note) [1] this bit determines the manual update for timer 0. 0 = no operation 1 = update tcntb0, tcmpb0 0 timer 0 start/stop [0] this bit determines start/stop for timer 0. 0 = stop 1 = start for timer 0 0 note: this bit has to be cleared at next writing.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-15 timer 0 count buffer register & com pare buffer register (tcntb0, tcmpb0) register address r/w description reset value tcntb0 0x4400000c r/w timer 0 count buffer register 0x00000000 tcmpb0 0x44000010 r/w timer 0 compare buffer register 0x00000000 tcmpb0 bit description initial state timer 0 compare buffer register [15:0] setting compare buffer value for timer 0 0x00000000 tcntb0 bit description initial state timer 0 count buffer register [15:0] setting count buffer value for timer 0 0x00000000 timer 0 count observation register (tcnto0) register address r/w description reset value tcnto0 0x44000014 r timer 0 count observation register 0x00000000 tcnto0 bit description initial state timer 0 observation register [15:0] setting count observation value for timer 0 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-16 timer 1 count buffer register & compare buffer register (tcntb1, tcmpb1) register address r/w description reset value tcntb1 0x44000018 r/w timer 1 count buffer register 0x00000000 tcmpb1 0x4400001c r/w timer 1 campare buffer register 0x00000000 tcmpb1 bit description initial state timer 1 compare buffer register [15:0] setting compare buffer value for timer 1 0x00000000 tcntb1 bit description initial state timer 1 count buffer register [15:0] setting count buffer value for timer 1 0x00000000 timer 1 count observation register(tcnto1) register address r/w description reset value tcnto1 0x44000020 r timer 1 count observation register 0x00000000 tcnto1 bit description initial state timer 1 observation register [15:0] setting count observation value for timer 1 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-17 timer 2 count buffer register & compare buffer register (tcntb2, tcmpb2) register address r/w description reset value tcntb2 0x44000024 r/w timer 2 count buffer register 0x00000000 tcmpb2 0x44000028 r/w timer 2 campare buffer register 0x00000000 tcmpb2 bit description initial state timer 2 compare buffer register [15:0] setting compare buffer value for timer 2 0x00000000 tcntb2 bit description initial state timer 2 count buffer register [15:0] setting count buffer value for timer 2 0x00000000 timer 2 count observation register (tcnto2) register address r/w description reset value tcnto2 0x4400002c r timer 2 count observation register 0x00000000 tcnto2 bit description initial state timer 2 observation register [15:0] setting count observation value for timer 2 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-18 timer 3 count buffer register & compare buffer register (tcntb3, tcmpb3) register address r/w description reset value tcntb3 0x44000030 r/w timer 3 count buffer register 0x00000000 tcmpb3 0x44000034 r/w timer 3 campare buffer register 0x00000000 tcmpb3 bit description initial state timer 3 compare buffer register [15:0] setting compare buffer value for timer 3 0x00000000 tcntb3 bit description initial state timer 3 count buffer register [15:0] setting count buffer value for timer 3 0x00000000 timer 3 count observation register (tcnto3) register address r/w description reset value tcnto3 0x44000038 r timer 3 count observation register 0x00000000 tcnto3 bit description initial state timer 3 observation register [15:0] setting count observation value for timer 3 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc mocroprocessor pwm timer 7-19 timer 4 count buffer register (tcntb4) register address r/w description reset value tcntb4 0x4400003c r/w timer 4 count buffer register 0x00000000 tcntb4 bit description initial state timer 4 count buffer register [15:0] setting count buffer value for timer 4 0x00000000 timer 4 count observation register (tcnto4) register address r/w description reset value tcnto4 0x44000040 r timer 4 count observation register 0x00000000 tcnto4 bit description initial state timer 4 observation register [15:0] setting count observation value for timer 4 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. pwm timer S3C24A0 risc microprocessor 7-20 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor watchdog timer 8-1 watchdog timer(preliminary) overview the S3C24A0 watchdog timer is used to resume the controller operation when it had been disturbed by malfunctions such as noise and system errors. it can be used as a normal 16-bit interval timer to request interrupt service. the watchdog timer generates the reset signal for 128 pclk cycles. features ? normal interval timer mode with interrupt request ? internal reset signal is activated for 128 pclk cycles when the timer count value reaches 0(time-out).
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. watchdog timer S3C24A0 risc microprocessor 8-2 watchdog timer operation the functional block diagram of the watchdog timer is show n in figure 8-1. the watchdog timer uses pclk as its only source clock. to generate the corresponding watchdog timer clock, the pclk frequency is prescaled first, and the resulting frequency is divided again. reset signal generator wtcnt (down counter) pcl k wtcon[4:3] wtdat reset 1/16 1/32 1/64 1/128 8-bit prescaler wtcon[15:8] wtcon[2] wtcon[0] interrupt mux figure 8-1. watchdog timer block diagram the prescaler value and the frequency division factor ar e specified in the watchdog timer control register, wtcon. the valid prescaler values range from 0 to 2 8 -1. the frequency division factor can be selected as 16, 32, 64, or 128. use the following equation to calculate the watchdog timer clock frequency and the duration of each timer clock cycle: t_watchdog = 1/( pclk / (prescaler value + 1) / division_factor ) wtdat & wtcnt when the watchdog timer is enabled first, the value of wtdat (watchdog timer data register) cannot be automatically reloaded into the wtcnt (timer counter). for this reason, an initial value must be written to the watchdog timer count register, wtcnt, before the watchdog timer starts. consideration of debugging environment when S3C24A0 is in debug mode using embedded ice, the watchdog timer must not operate. the watchdog timer can determine whether or not t he current mode is the debug mode from the cpu core signal (dbgack signal). once the dbgack signal is asserted, the reset output of the watchdog timer is not activated when the watchdog timer is expired.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor watchdog timer 8-3 watchdog timer special registers watchdog timer control register (wtcon) using the watchdog timer control register, wtcon, you can enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output. the watchdog timer is used to resume the S3C24A0 restart on mal-function after power-on; if controller restart is not desired, the watchdog timer should be disabled. if the user wants to use the normal timer provided by the watchdog timer, please enable the interrupt and disable the watchdog timer. register address r/w description reset value wtcon 0x44100000 r/w watchdog timer control register 0x8021 wtcon bit description initial state prescaler value [15:8] the prescaler value the valid range is from 0 to (2 8 -1) 0x80 reserved [7:6] reserved. these two bits must be 00 in normal operation. 00 watchdog timer [5] enable or disable bit of watchdog timer. 0 = disable 1 = enable 1 clock select [4:3] this two bits determines the clock division factor 00 : 16 01 : 32 10 : 64 11 : 128 00 interrupt generation [2] enable or disable bit of the interrupt. 0 = disable 1 = enable 0 reserved [1] reserved. this bit must be 0 in normal operation 0 reset enable/disable [0] enable or disable bit of watchdog timer output for reset signal 1 : asserts reset signal of the S3C24A0 at watchdog time-out 0 : disables the reset function of the watchdog timer. 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. watchdog timer S3C24A0 risc microprocessor 8-4 watchdog timer data register (wtdat) the watchdog timer data register, wtdat is used to specif y the time-out duration. the content of wtdat can not be automatically loaded into the timer counter at initial watchdog timer operation. however, the first time-out occurs by using 0x8000(initial value), after then the value of wtdat will be automatically reloaded into wtcnt. register address r/w description reset value wtdat 0x44100004 r/w watchdog timer data register 0x8000 wtdat bit description initial state count reload value [15:0] watchdog timer count value for reload. 0x8000 watchdog timer count register (wtcnt) the watchdog timer count register, wtcnt, contains the current count values for the watchdog timer during normal operation. note that the content of the watc hdog timer data register cannot be automatically loaded into the timer count register when the watchdog timer is enabled initially, so the watchdog timer count register must be set to an initial value before enabling it. register address r/w description reset value wtcnt 0x44100008 r/w watchdog timer count register 0x8000 wtcnt bit description initial state count value [15:0] the current count value of the watchdog timer 0x8000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-1 dma (preliminary) overview S3C24A0 supports four-channel dma( bridge dma or peripher al dma) controller that is located between the system bus and the peripheral bus. each channel of dma controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions. in other words, each channel can handle the following four cases: 1) both source and destination are in the system bus, 2) source is in the system bus while destination is in the peripheral bus, 3) source is in the peripheral bus while destination is in the system bus, 4) both source and destination are in the peripheral bus. the main advantage of dma is that it can transfer the data without cpu in tervention. the operation of dma can be initiated by s/w, the request from inter nal peripherals or the external request pins.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. dma S3C24A0 risc microprocessor 9-2 dma request sources each channel of dma controller can select one of dm a request source among four dma sources if h/w dma request mode is selected by dcon register. (note that if s/w request mode is selected, this dma request sources have no meaning at all.) the four dma sources for each channel are as follows. source0 source1 source2 source3 source4 source5 source6 source7 ch-0 nxdreq0 uart0 i2ssdi pwm timer usb device ep1 ac97_pcmout mstick irda ch-1 nxdreq1 uart1 i2ssdo spi usb device ep2 ac97_pcmin ac97_pcmout irda ch-2 uart0 i2ssdo sdmmc pwm timer usb device ep3 ac97_micin ac97_pcmin reserved ch-3 uart1 sdmmc spi timer usb device ep4 mstick ac97_micin reserved table 9-1. dma request sources for each channel here, nxdreq0 and nxdreq1 represent two external sources(external devices), and i2ssdo and i2ssdi represent iis transmitting and receiving, respectively. dma operation the details of dma operation can be explained using three-state fsm(fi nite state machine) as follows: state-1. as an initial state, it waits for the dma request. if it comes, go to state-2. at this state, dma ack and int req are 0. state-2. in this state, dma ack becomes 1 a nd the counter(curr_tc) i s loaded from dcon[19:0] register. note that dma ack becomes 1 and remains 1 until it is cleared later. state-3. in this state, sub-fsm handling the atomic oper ation of dma is initiat ed. the sub-fsm reads the data from the source address and then writes it to destination address. in this operation, data size and transfer size (single or burst) are considered. this operation is repeated until the counter(curr_tc) becomes 0 in the whole service mode, while performed only once in a single service mode. the main fsm (this fsm) count s down the curr_tc when the sub-fsm finishes each of atomic operation. in addi tion, this main fsm asserts the int req signal when curr_tc becomes 0 and the interrupt setting of dcon[28] regist er is set to 1. in addition, it clears dma ack if one of the following conditions are met. 1) curr_tc becomes 0 in the whole service mode 2) atomic operation finishes in the single service mode. note that in the single service mode, these three states of main fsm are performed and then stops, and waits for another dma req. and if dma req comes in all three states are repeated. theref ore, dma ack is asserted and then de-asserted for each atomic transfer. in contrast, in the whole service mode, main fsm waits at state-3 until curr_tc becomes 0. therefore, dma ack is a sserted during all the transfers and then de-asserted when tc reaches 0. however, int req is asserted only if curr_tc becomes 0 regardless of the service mode (single service mode or whole service mode).
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-3 external dma dreq/dack protocol there are four types of external dma request/acknowl edge protocols. each type defines how the signals like dma request and acknowledge are related to these protocols. basic dma timing the dma service means paired reads and writes cycles during dma operation, which is one dma operation. the fig. 9-1 shows the basic timing in the dma operation of the S3C24A0. - the setup time and the delay time of xnx dreq and xnxdack are same in all the modes. - if the completion of xnxdreq meets its setup time, it is synchronized twice and then xnxdack is asserted. - after assertion of xnxdack, dma requests the bus and if it gets the bus it performs its operations. xnxdack is deasserted when dma operation finishes. xsclk 9.3ns setup 9.3ns setup 6.8ns delay 6.6ns delay read write min. 2mclk xnxdreq xnxdack min. 3mclk figure 9-1. basic dma timing diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. dma S3C24A0 risc microprocessor 9-4 demand/handshake mode comparison ? related to the protocol between xnxdreq and xnxdack these are two different modes related to the protoc ol between xnxdreq and xnxdack. fig. 8-2 shows the differences between these two modes i.e., demand and handshake modes. at the end of one transfe r(single/burst transfer), dma checks the state of doubl e-synched xnxdreq. demand mode - if xnxdreq remains asserted, the next transfer star ts immediately. otherwise it waits for xnxdreq to be asserted. handshake mode - if xnxdreq is deasserted, dma deasserts xnxdack in 2cycles. otherwise it waits until xnxdreq is deasserted. caution : xnxdreq has to be asserted(low) only after the deassertion(high) of xnxdack. demand mode xsclk xnxdack xnxdack xnxdreq xnxdreq 2cycles double synch read write read write handshake mode bus acquisiton actual transfer 1st transfer 2nd transfer 2cycles read write double synch 2cycles figure 9-2. demand/handshake mode comparison
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-5 transfer size - there are two different transfer sizes; single and burst 4. - dma holds the bus firmly during t he transfer of these chunk of data, thus other bus masters can not get the bus. burst 4 transfer size 4 sequential reads and 4 sequential writes are performed in the burst 4 transfer. * note: single transfer size : one read and one write are performed. xsclk xnxdreq xnxdack read read read write write write read write 3 cycles double synch figure 9-3. burst 4 transfer size
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. dma S3C24A0 risc microprocessor 9-6 examples of possible cases single service, demand mode, single transfer size the assertion of xnxdreq is need for every unit transfer( single service mode), the operation continues while the xnxdreq is asserted(demand mode), and one pair of read and write(single transfer size) is performed. xsclk xnxdreq xnxdack xsclk xnxdreq xnxdack read write read write double synch figure 9-4. single service, dema nd mode, single transfer size single service/handshake mode, single transfer size xnxdreq xnxdack xsclk read write read write 2cycles double synch figure 9-5. single service, handsh ake mode, single transfer size whole service/handshake mode, single transfer size xsclk xnxdreq xnxdack read write read write read write 2cycles 2cycles 3 cycles double synch figure 9-6. whole service, handshake mode, single transfer size
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-7 dma special registers there are seven control registers for each dma channel. (since there are four channels, the total number of control registers is 28.) four of them are to control the dma transfer, and other three are to see the status of dma controller. the details of those registers are as follows. dma initial source register (disrc) register address r/w description reset value disrc0 0x40400000 r/w dma0 initial source register 0x00000000 disrc1 0x40500000 r/w dma1 initial source register 0x00000000 disrc2 0x40600000 r/w dma2 initial source register 0x00000000 disrc3 0x40700000 r/w dma3 initial source register 0x00000000 disrcn bit description initial state s_addr [30:0] these bits are the base address (start address) of source data to transfer. this value will be loaded into curr_src only if the curr_src is 0 and the dma ack is 1. 0x00000000 dma initial source control register (disrcc) register address r/w description reset value disrcc0 0x40400004 r/w dma0 initial source control register 0x00000000 disrcc1 0x40500004 r/w dma1 initial source control register 0x00000000 disrcc2 0x40600004 r/w dma2 initial source control register 0x00000000 disrcc3 0x40700004 r/w dma3 initial source control register 0x00000000 disrcn bit description initial state loc [1] bit 1 is used to select the location of source. 0: the source is in the system bus (ahb), 1: the source is in the peripheral bus (apb) 0 inc [0] bit 0 is used to select the address increment. 0 = increment 1= fixed if it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. if it is 1, the address is not changed after the transfer (in the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer). 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. dma S3C24A0 risc microprocessor 9-8 dma initial destination register (didst) register address r/w description reset value didst0 0x40400008 r/w dma0 initial destination register 0x00000000 didst1 0x40500008 r/w dma1 initial destination register 0x00000000 didst2 0x40600008 r/w dma2 initial destination register 0x00000000 didst3 0x40700008 r/w dma3 initial destination register 0x00000000 didstn bit description initial state d_addr [30:0] these bits are the base address (start address) of destination for the transfer. this value will be loaded into curr_src only if the curr_src is 0 and the dma ack is 1. 0x00000000 dma initial destination c ontrol register (didstc) register address r/w description reset value didstc0 0x4040000c r/w dma0 initial destination control register 0x00000000 didstc1 0x4050000c r/w dma1 initial destination control register 0x00000000 didstc2 0x4060000c r/w dma2 initial destination control register 0x00000000 didstc3 0x4070000c r/w dma3 initial destination control register 0x00000000 didstn bit description initial state chk_int [2] select interrupt occurrence time when auto reload is setting 0: interrupt will occur when tc reaches 0 1: interrupt will occur after auto reload is performed. 0 loc [1] bit 1 is used to select the location of destination. 0: the destination is in the system bus (ahb). 1: the destination is in the peripheral bus (apb). 0 inc [0] bit 0 is used to select the address increment. 0 = increment 1= fixed if it is 0, the address is increased by its data size after each transfer in burst and single transfer mode. if it is 1, the address is not changed after the transfer (in the burst mode, address is increased during the burst transfer, but the address is recovered to its first value after the transfer). 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-9 dma control register (dcon) register address r/w description reset value dcon0 0x40400010 r/w dma0 control register 0x00000000 dcon1 0x40500010 r/w dma1 control register 0x00000000 dcon2 0x40600010 r/w dma2 control register 0x00000000 dcon3 0x40700010 r/w dma3 control register 0x00000000 dconn bit description initial state dmd_hs [31] select one between demand mode and handshake mode. 0 : demand mode is selected 1 : handshake mode is selected. in both modes, dma controller starts its transfer and asserts dack for a given asserted dreq. the difference between two modes is whether it waits for the de-asse rted dack or not. in handshake mode, dma controller waits for the de- asserted dreq before starting a new transfer. if it sees the de-asse rted dreq, it de- asserts dack and waits for another asserted dreq. in contrast, in the demand mode, dma controller does not wait until t he dreq is de-asserted. it just de- asserts dack and then starts another transfer if dreq is asserted. we recommend using handshake mode for external dma request sources to prevent unintended starts of new transfers. 0 sync [30] select dreq/dack synchronization. 0: dreq and dack are synchroni zed to pclk (apb clock). 1: dreq and dack are synchronized to hclk (ahb clock). therefore, devices attached to ahb system bus, this bit has to be set to 1, while those attached to apb syst em, it should be set to 0. for the devices attached to external system, user should select this bit depending on whether the external system is synchronized with ahb system or apb system. 0 int [29] enable/disable the interrupt setting for curr_tc(terminal count) 0: curr_tc interrupt is disabled. user has to look the transfer count in the status register. (i.e., polling) 1: interrupt request is generated when all the transfer is done (i.e., curr_tc becomes 0). 0 tsz [28] select the transfer size of an atomic transfer (i.e., transfer performed at each time dma owns the bus before releasing the bus). 0: a unit transfer is performed. 1: a burst transfer of length four is performed. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. dma S3C24A0 risc microprocessor 9-10 dconn bit description initia l stat e servmode [27] select the service mode between single service mode and whole service mode. 0: single service mode is selected in which after each atomic transfer (single or burst of length four) dma st ops and waits for another dma request. 1: whole service mode is selected in which one request gets atomic transfers to be repeated until the transfer count reaches to 0. in this mode, additional request is not required. here, note that even in the whole service mode, dma releases the bus after each atomic trans fer and then tries to re-get the bus to prevent starving of other bus masters. 0 hwsrcsel [26:24] select dma request source for each dma. source 0 source1 source 2 sourc e3 source 4 source 5 source 6 source 7 ch- 0 nxdre q0 uart0 i2ssdi pwm timer usb device ep1 ac97_ pcmout mstick irda ch- 1 nxdre q1 uart1 i2ssdo spi usb device ep2 ac97_ pcmin ac97_ pcmout irda ch- 2 uart0 i2ssdo sd mmc pwm timer usb device ep3 ac97_ micin ac97_ pcmin reserve d ch- 3 uart1 sd mmc spi timer usb device ep4 mstick ac97_ micin reserve d this bits control the 8-1 mux to select the dma request source of each dma. these bits have meanings if and only if h/w request mode is selected by dconn[23]. 000 swhw_sel [23] select the dma source between software (s/w request mode) and hardware (h/w request mode). 0: s/w request mode is selected and dma is triggered by setting sw_trig bit of dmasktrig control register. 1: dma source selected by bit[25:24] is used to trigger the dma operation. 0 reload [22] set the reload on/off option. 0: auto reload is performed when a current value of transfer count becomes 0 (i.e., all the required transfers are performed). 1: dma channel(dma req) is turned off when a current value of transfer count becomes 0. the channel on/off bit(dmasktrign[1]) is set to 0(dreq off) to prevent unintended further start of new dma operation 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-11 dsz [21:20] data size to be transferred. 00 = byte 01 = half word 10 = word 11 = reserved 00 tc [19:0] initial transfer count (or transfer beat). note that the actual number of bytes t hat are transferred is computed by the following equation: dsz x tsz x tc, wher e dsz, tsz, and tc represent data size (dconn[21:20]), transfer size (dconn[28]), and initial transfer count, respectively. this value will be loaded into curr_tc only if the curr_tc is 0 and the dma ack is 1. 0000 0 dma status register (dstat) register address r/w description reset value dstat0 0x40400014 r dma0 count register 000000h dstat1 0x40500014 r dma1 count register 000000h dstat2 0x40600014 r dma2 count register 000000h dstat3 0x40700014 r dma3 count register 000000h dstatn bit description initial state stat [21:20] status of this dma controller. 00: it indicates that dma controller is ready for another dma request. 01: it indicates that dma controller is busy for transfers. 00b curr_tc [19:0] current value of transfer count. note that transfer count is initia lly set to the value of dconn[19:0] register and decreased by one at the end of every atomic transfer. 00000h
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. dma S3C24A0 risc microprocessor 9-12 dma current source register (dcsrc) register address r/w description reset value dcsrc0 0x40400018 r dma0 current source register 0x00000000 dcsrc1 0x40500018 r dma1 current source register 0x00000000 dcsrc2 0x40600018 r dma2 current source register 0x00000000 dcsrc3 0x40700018 r dma3 current source register 0x00000000 dcsrcn bit description initial state curr_src [30:0] current source address for dman. 0x00000000 current destination register (dcdst) register address r/w description reset value dcdst0 0x4040001c r dma0 current destination register 0x00000000 dcdst1 0x4050001c r dma1 current destination register 0x00000000 dcdst2 0x4060001c r dma2 current destination register 0x00000000 dcdst3 0x4070001c r dma3 current destination register 0x00000000 dcdstn bit description initial state curr_dst [30:0] current destination address for dman. 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor dma 9-13 dma mask trigger register (dmasktrig) register address r/w description reset value dmasktrig0 0x40400020 r/w dma0 mask trigger register 000 dmasktrig1 0x40500020 r/w dma1 mask trigger register 000 dmasktrig2 0x40600020 r/w dma2 mask trigger register 000 dmasktrig3 0x40700020 r/w dma3 mask trigger register 000 dmasktrign bit description initial state stop [2] stop the dma operation. 1: dma stops as soon as the current atomic transfer ends. if there is no current running atomic transfer, dma stops immediately. the curr_tc, curr_src, curr_dst will be 0. note: due to possible current atomic transfer, ?stop? may take several cycles. the finish of ?s topping? operation (i.e., actual stop time) can be detected by wait ing until the channel on/off bit(dmasktrign[1]) is set to off. this stop is ?actual stop?. 0 on_off [1] dma channel on/off bit. 0: dma channel is turned off. (dma request to this channel is ignored.) 1: dma channel is turned on and the dma request is handled. this bit is automatically set to off if we set the dconn[22] bit to ?no auto reload? and/or stop bit of dmasktrign to ?stop?. note that when dcon[22] bit is "no auto reload", this bit becomes 0 when curr_tc reaches 0. if the stop bit is 1, this bit becomes 0 as soon as the current atomic transfer finishes. note. this bit should not be changed manually during dma operations (i.e., this has to be changed only by using dcon[22] or stop bit.) 0 sw_trig [0] trigger the dma channel in s/w request mode. 1: it requests a dma operation to this controller. however, note that for this trigger to have effects s/w request mode has to be selected (dconn[23]) and channel on_off bit has to be set to 1 (channel on). when dma operation starts, this bit is cleared automatically. 0 note. you can freely change the values of disrc register, didst registers, and tc field of dcon register. those changes take effect only after the finish of curr ent transfer (i.e., when curr_tc becomes 0). on the other hand, any change made to other registers and/or fields ta kes immediate effect. therefore, be careful in changing those registers and fields.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor real time clock 10-1 rtc (real time clock)(preliminary) overview the rtc (real time clock) unit can be operated by the ba ckup battery while the system power is off. the rtc can transmit 8-bit data to cpu as bcd (binary coded decimal) values using the strb/ldrb arm operation. the data include second, minute, hour, date, day, month, and year. the rtc unit works with an external 32.768 khz crystal and also can perform the alarm function. feature ? bcd number : second, minute, hour, date, day, month, year ? leap year generator ? alarm function : alarm interrupt or wake-up from power down mode. ? year 2000 problem is removed. ? independent power pin (rtcvdd) ? supports millisecond tick time interrupt for rtos kernel time tick. ? round reset function
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. real time clock S3C24A0 risc microprocessor 10-2 real time clock operation 2 15 cl o c k di v i d e r x to rtc x ti r t c co n t r o l re g i s t e r sec m in hour dat e day m on year leap year gener at or al a r m ge n e r a t o r re s e t re g i s t e r 1 h z a lm in t r tc c o n r tc a lm r tc r s t ti m e ti ck gener at or ti m e ti c k ti c n t 128 h z p m w k u p p w d n figure 10-1. real time clock block diagram leap year generator this block can determine whether the last date of each month is 28, 29, 30, or 31, based on data from bcddate, bcdmon, and bcdyear. this block considers the leap year in deciding on the last date. an 8-bit counter can only represent 2 bcd digits, so it c annot decide whether 00 year is a leap y ear or not. for example, it can not discriminate between 1900 and 2000. to solve this problem, the rtc block in S3C24A0 has hard-wired logic to support the leap year in 2000. please note 1900 is not leap y ear while 2000 is leap year. therefore, two digits of 00 in S3C24A0 denote 2000, not 1900. read/write registers bit 0 of the rtccon register must be set to high in order to write the bcd register in rtc block. to display the sec., min., hour, date, month, and year, the cpu should read the data in bcdsec, bcdmin, bcdhour, bcdday, bcddate, bcdmon, and bcdyear registers, respectively, in the rtc block. however, a one second deviation may exist because multiple registers are read. for example, when the user reads the registers from bcdyear to bcdmin, the result is assum ed to be 2059(year), 12(month), 31(date), 23(hour) and 59(minute). when the user read the bcdsec register and the result is a value from 1 to 59(second), there is no problem, but, if the result is 0 sec., the year, month, date, hour, and minute may be changed to 2060(year), 1(month), 1(date), 0(hour) and 0(minute) because of the one second deviation that was mentioned. in this case, user should re-read from bcdyear to bcdsec if bcdsec is zero. backup battery operation the rtc logic can be driven by the backup battery, whic h supplies the power through the rtcvdd pin into rtc block, even if the sy stem power is off. when the system off, the interfaces of the cpu and rtc logic should be blocked, and the backup battery only drives the osc illation circuit and the bcd counters to minimize power dissipation.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor real time clock 10-3 2003-01-15 alarm function the rtc generates an alarm signal at a specified time in the power down mode or normal operation mode. in normal operation mode, the alarm interrupt (almint) is activated. in the power down mode the power management wakeup (pmwkup) signal is activated as we ll as the almint. the rtc alarm register, rtcalm, determines the alarm enable/disable and t he condition of the alarm time setting. tick time interrupt the rtc tick time is used for interrupt request. the ticnt register has an interrupt enable bit and the count value for the interrupt. the count value reaches '0' when the tick ti me interrupt occurs. then the period of interrupt is as follow: period = ( n+1 ) / 128 second n : tick time count value (1~127) this rtc time tick may be used for rtos(real time operati ng system) kernel time tick. if time tick is generated by rtc time tick, the time related function of rt os will always synchronized with real time. round reset function the round reset function can be performed by the rt c round reset register, rtcrst. the round boundary (30, 40, or 50 sec) of the second carry generation can be selected, and the second value is rounded to zero in the round reset. for example, when the current time is 23:37:47 and the round boundary is selected to 40 sec, the round reset changes the current time to 23:38:00. note all rtc registers have to be access ed by the byte unit using the strb ,ldrb instructions or char type pointer. 32.768khz x-tal connection example the figure 10-2 is an example circuit of the rtc unit oscillation at 32.768khz. xtirtc xtortc 32768hz 15~ 22pf figure 10-2. main oscillator circuit examples
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. real time clock S3C24A0 risc microprocessor 10-4 real time clock special registers real time clock control register (rtccon) the rtccon register consists of 4 bits such as the rtcen, which controls the read/write enable of the bcd registers, clksel, cntsel, and clkrst for testing. rtcen bit can control all interfaces between the cpu and the rtc, so it should be set to 1 in an rtc control routine to enable data read/write after a system reset. also before power off, the rtcen bit should be cleared to 0 to prevent inadvertent writing into rtc registers. register address r/w description reset value rtccon 0x44200040 r/w (by byte) rtc control register 0x0 rtccon bit description initial state clkrst [3] rtc clock count reset 0 = no reset, 1 = reset 0 cntsel [2] bcd count select 0 = merge bcd counters 1 = reserved (separate bcd counters) 0 clksel [1] bcd clock select 0 = xtal 1/2 15 divided clock 1 = reserved (xtal clock only for test) 0 rtcen [0] rtc control enable 0 = disable note : only bcd time count and read operation can be performed. 1 = enable 0 notes: 1. all rtc registers have to be accessed by byte unit using strb and ldrb instructions or char type pointer. tick time count register (ticnt) register address r/w description reset value ticnt 0x44200044 r/w (by byte) tick time count register 0x0 ticnt bit description initial state tick int enable [7] tick time interrupt enable 0 = disable 1 = enable 0 tick time count [6:0] tick time count value. (1~127) this counter value decreases internally, and users can not read this real counter value in working. 000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor real time clock 10-5 2003-01-15 rtc alarm control register (rtcalm) rtcalm register determines the alar m enable and the alarm time. note that the rtcalm register generates the alarm signal through both almint and pmwkup in power down mode, but only through almint in the normal operation mode. register address r/w description reset value rtcalm 0x44200050 r/w (by byte) rtc alarm control register 0x0 rtcalm bit description initial state reserved [7] reserved 0 almen [6] alarm global enable 0 = disable, 1 = enable 0 yearen [5] year alarm enable 0 = disable, 1 = enable 0 monren [4] month alarm enable 0 = disable, 1 = enable 0 dateen [3] date alarm enable 0 = disable, 1 = enable 0 houren [2] hour alarm enable 0 = disable, 1 = enable 0 minen [1] minute alarm enable 0 = disable, 1 = enable 0 secen [0] second alarm enable 0 = disable, 1 = enable 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. real time clock S3C24A0 risc microprocessor 10-6 alarm second data register (almsec) register address r/w description reset value almsec 0x44200054 r/w (by byte) alarm second data register 0x0 almsec bit description initial state reserved [7] reserved 0 secdata [6:4] bcd value for alarm second from 0 to 5 000 [3:0] from 0 to 9 0000 alarm min data register (almmin) register address r/w description reset value almmin 0x44200058 r/w (by byte) alarm minute data register 0x00 almmin bit description initial state reserved [7] reserved 0 mindata [6:4] bcd value for alarm minute from 0 to 5 000 [3:0] from 0 to 9 0000 alarm hour data register (almhour) register address r/w description reset value almhour 0x4420005c r/w (by byte) alarm hour data register 0x0 almhour bit description initial state reserved [7:6] reserved 00 hourdata [5:4] bcd value for alarm hour from 0 to 2 00 [3:0] from 0 to 9 0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor real time clock 10-7 2003-01-15 alarm date data register (almdate) register address r/w description reset value almdate 0x44200060 r/w (by byte) alarm date data register 0x01 almdate bit descript ion initial state reserved [7:6] reserved 00 datedata [5:4] bcd value for alarm date, from 0 to 28, 29, 30, 31 from 0 to 3 00 [3:0] from 0 to 9 0001 alarm mon data register (almmon) register address r/w description reset value almmon 0x44200064 r/w (by byte) alarm month data register 0x01 almmon bit description initial state reserved [7:5] reserved 00 mondata [4] bcd value for alarm month from 0 to 1 0 [3:0] from 0 to 9 0001 alarm year data register (almyear) register address r/w description reset value almyear 0x44200068 r/w (by byte) alarm year data register 0x0 almyear bit descript ion initial state yeardata [7:0] bcd value for year from 00 to 99 0x0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. real time clock S3C24A0 risc microprocessor 10-8 rtc round reset register (rtcrst) register address r/w description reset value rtcrst 0x4420006c r/w (by byte) rtc round reset register 0x0 rtcrst bit description initial state srsten [3] round second reset enable 0 = disable, 1 = enable 0 seccr [2:0] round boundary for second carry generation. 011 = over than 30 sec 100 = over than 40 sec 101 = over than 50 sec note : if other values(0,1,2,6,7) are set, no second carry is generated. but second value can be reset. 000 bcd second register (bcdsec) register address r/w description reset value bcdsec 0x44200070 r/w (by byte) bcd second register undefined bcdsec bit description initial state secdata [6:4] bcd value for second from 0 to 5 - [3:0] from 0 to 9 - bcd minute register (bcdmin) register address r/w description reset value bcdmin 0x44200074 r/w (by byte) bcd minute register undefined bcdmin bit description initial state mindata [6:4] bcd value for minute from 0 to 5 - [3:0] from 0 to 9 -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor real time clock 10-9 2003-01-15 bcd hour register (bcdhour) register address r/w description reset value bcdhour 0x44200078 r/w (by byte) bcd hour register undefined bcdhour bit description initial state reserved [7:6] reserved - hourdata [5:4] bcd value for hour from 0 to 2 - [3:0] from 0 to 9 - bcd date register (bcddate) register address r/w description reset value bcddate 0x4420007c r/w (by byte) bcd date register undefined bcddate bit description initial state reserved [7:6] reserved - datedata [5:4] bcd value for date from 0 to 3 - [3:0] from 0 to 9 - bcd day register (bcdday) register address r/w description reset value bcdday 0x44200080 r/w (by byte) bcd day register undefined bcdday bit description initial state reserved [7:3] reserved - daydata [2:0] bcd value for day from 1 to 7 -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. real time clock S3C24A0 risc microprocessor 10-10 bcd month register (bcdmon) register address r/w description reset value bcdmon 0x44200084 r/w (by byte) bcd month register undefined bcdmon bit description initial state reserved [7:5] reserved - mondata [4] bcd value for month from 0 to 1 - [3:0] from 0 to 9 - bcd year register (bcdyear) register address r/w description reset value bcdyear 0x44200088 r/w (by byte) bcd year register undefined bcdyear bit description initial state yeardata [7:0] bcd value for year from 00 to 99 -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-1 uart(preliminary) overview the S3C24A0 uart (universal asynchronous re ceiver and transmitter) unit provides two independent asynchronous serial i/o (sio) ports, each of which c an operate in interrupt-based or dma-based mode. in other words, uart can generate an interrupt or dma reques t to transfer data between cpu and uart. it can support bit rates of up to 115.2k bps, when uart use system clock. if external dev ice provides uart with uclk, then uart can operates at more higher speed. each uart channel contains two 64-byte fifos for receiver and transmitter. the S3C24A0 uart includes programmable baud-rates, infrared (ir) transmit/receive, one or two stop bit insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking. each uart contains a baud-rate generator, transmitter, receiver and control unit, as shown in figure11-1. the baud-rate generator can be clocked by pclk. the trans mitter and the receiver cont ain 64-byte fifos and data shifters. data, which is to be transmitted, is written to fifo and then copied to the transmit shifter. it is then shifted out by the transmit data pin (txdn). the receiv ed data is shifted from the receive data pin (rxdn), and then copied to fifo from the shifter. features ? rxd0, txd0, rxd1, txd1 with dm a-based or interrupt-based operation ? uart ch 0, 1 with irda 1.0 & 64-byte fifo ? uart ch 0, 1 with nrts 0, ncts0, nrts1, ncts1 ? supports handshake transmit / receive
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-2 block diagram buad-rate generator control unit transmitter receiver peripheral bus txdn clock source rxdn transmit fifo register (fifo mode) transmit holding register (non-fifo mode) receive fifo register (fifo mode) receive holding register (non-fifo mode only) in fifo mode, all 64 byte of buffer register are used as fifo register. in non-fifo mode, only 1 byte of buffer register is used as holding register. transmit shifter transmit buffer register(64 byte) receive shifter receive buffer register(64 byte) figure 11-1. uart block diagram (with fifo)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-3 uart operation the following sections describe the uart operations t hat include data transmission, data reception, interrupt generation, baud-rate generation, loopback mode, infrared mode, and auto flow control. data transmission the data frame for transmission is programmable. it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits, which can be specified by the li ne control register (ulconn). the transmitter can also produce the break condition. the break condition forces the serial output to l ogic 0 state for one frame transmission time. this block transmits break signal after the present transmission word transmits perfectly. after the break signal transmission, it conti nously transmits data into the tx fifo (tx holding register in the case of non-fifo mode). data reception like the transmission, the data frame for reception is also programmable. it cons ists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 stop bits in the line control register (ulconn). the receiver can detect overrun error. the overrun error indicates that new data has overwritten the ol d data before the old data has been read. receive time-out condition occurs when it does not receive data during the 3 wo rd time (this interval follows the setting of word length bit) and the rx fifo is not empty in the fifo mode. auto flow control(afc) S3C24A0's uart 0 and uart 1 support auto flow control wi th nrts and ncts signals, in case, it would have to connect uart to uart. if users connect uart to a modem , disable auto flow control bit in umconn register and control the signal of nrts by software. in afc, nrts is controlled by condi tion of the receiver and operation of transmitter is controlled by the ncts signal. the uart's transmitter transfers the data in fi fo only when ncts signal active (in afc, ncts means that the other uart's fifo is ready to receive data). before the uart receives data, nrts has to be activated when its receive fifo has a spare more than 32-byte and has to be inactivated when its receive fifo has a spare under 32-byte (in afc, nrts means that its own receive fifo is ready to receive data). rxd nrts uart a txd ncts uart b txd ncts uart a rxd nrts uart b transmission case in uart a reception case in uart a figure 11-2. uart afc interface
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-4 non auto-flow control (controlling nrts and ncts by s/w) example rx operation with fifo 1. select receive mode(interrupt or dma mode) 2. check the value of rx fifo count in ufstatn register. if the value is less than 32 , users have to set the value of umconn[0] to '1'(activate nrts ), and if it is equal or larger than 32, users have to set the value to '0'(inactivate nrts). 3. repeat step 2. tx operation with fifo 1. select transmit mode (interrupt or dma mode) 2. check the value of umstatn[0]. if the value is '1'(ncts is activated), users write the data to tx fifo register.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-5 rs-232c interface if users connect to modem interface (not equal null modem), nrts, ncts, ndsr , ndtr, dcd and nri signals are need. in this case, users control these signals with general i/o ports by s/w because the afc does not support the rs-232c interface. interrupt/dma request generation each uart of S3C24A0 has four status (tx/rx/error) signals: overrun error, receive buffer data ready, transmit buffer empty, and transmit shifter empty, all of which are indicated by the corres ponding uart status register (utrstatn/uerstatn). the overrun error can cause the receiv e error status interrupt request, if t he receive-error-status-interrupt-enable bit is set to one in the control register, uconn. when the receiver transfers the data of the receive shifter to the receive fifo register in fifo mode and the number of received data reaches rx fi fo trigger level, rx interrupt is generated, if receive mode in control register(uconn) is selected as 1(interrupt request or polling mode). in the non-fifo mode, transfering the data of the receive shifter to the receive holding register will cause rx interrupt under the interrupt request and polling mode. when the transmitter transfers data from its transmit fifo register to its transmit shifter and the number of data left in transmit fifo reaches tx fifo trigger level, tx interrupt is generated, if trans mit mode in control register is selected as interrupt request or polling mode. in the non-fifo mode, transfering data from the transmi t holding register to the transmit shifter will cause tx interrupt under the interrupt request and polling mode. if the receive mode and transmit mode in control regist er are selected as the dman request mode then dman request is occurred instead of rx or tx interrupt in the situation mentioned above. table 11-1. interrupts in connection with fifo type fifo mode non-fifo mode rx interrupt each time receive data reaches the trigger level of receive fifo, the rx interrupt will be generated. when the number of data in fifo does not reaches rx fifo trigger level and does not receive data during 3 word time(this interval follows the setting of word length bit), the rx interrupt will be generated(receive time out). each time receive data becomes full, the receive holding register generates an interrupt. tx interrupt each time transmit data reaches the trigger level of transmit fifo(tx fifo trigger level), the tx interrupt will be generated. each time transmit data become empty, the transmit holding register generates an interrupt. error interrupt overrun error will be generated, when it gets to the top of the receive fifo without reading out data in it. overrun error generates an error interrupt immediately.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-6 uart error status fifo uart has the error status fi fo besides the rx fifo register. the erro r status fifo indicates which data, among fifo registers, is received with an error. the error interrupt will be iss ued only when the data, which has an error, is ready to read out. to clear the error status fifo , the urxhn with an error and uerstatn must be read out. for example, it is assumed that the uart rx fi fo receives a, b, c, d,and e char acters sequentially and the frame error occurs while receiving 'b', and the par ity error occurs while receiving 'd'. the actual uart receive error will not generate any error interrupt because the character, which was received with an error, has not been read yet. the error interrupt will occur when the character is read out. figure 11-3 shows the uart receiving the fi ve characters including the two errors. time sequence flow error interrupt note #0 when no character is read out - #1 a, b, c, d, and e is received - #2 after a is read out the frame error (in b) interrupt occurs. the 'b' has to be read out. #3 after b is read out - #4 after c is read out the parity error (in d) interrupt occurs. the 'd' has to be read out. #5 after d is read out - #6 after e is read out - - - - - - - - - - - - 'e' 'd' 'c' 'b' 'a' rx fifo urxhn uerstatn break error parity error frame error error status generator unit error status fifo figure 11-3. example showing uart r eceiving 5 characters with 2 errors
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-7 baud-rate generation each uart's baud-rate generator provides the serial clock for transmitter and receiver. the source clock for the baud-rate generator can be selected with the S3C24A0's inte rnal system clock or uclk. in other words, dividend can be selected by the setting of cl ock selection of uconn. the baud-rat e clock is generated by dividing the source clock(pclk or uclk) by 16 and a 16-bit diviso r specified in the uart baud-rate divisor register (ubrdivn). the ubrdivn c an be determined as follows: ubrdivn = (int)(pclk/(bps x 16) ) -1 where the ubrdivn should be from 1 to (2 16 -1). for the accurate uart operation, s3c 24a0 also supports uartclk as a dividend. if uartclk, supplied by external ua rt device or system, is used, then serial clock of uart is exactly synchronized with uartclk. so, user can get the more precision uart operat ion. the ubrdivn can be determined as follows: ubrdivn = (int)( uartclk / (bps x 16) ) ?1 where the ubrdivn should be from 1 to (2 16 -1) and uartclk should be smaller than pclk. for example, if the baud-rate is 115200 bps and pclk or uartclk is 40 mhz , ubrdivn is: ubrdivn = (int)(40000000/(115200 x 16) ) -1 = (int)(21.7) -1 = 22 -1 = 21 baud-rate error tolerance uart frame error should be less than 1.87%(3/160). tupclk = (ubrdivn + 1) x 16 x 10 / pclk tupclk : real uart clock time tuexact = 10 / baud-rate tuexact : ideal uart clock time uart error = (tupclk ? tuexact) / tuexact x 100% note. 1. 1frame = 1start bit + 8 data bit + 1 stop bit. 2. in specific condition, we can support bit rates up to 921.6k bps. for example, w hen pclk is 60mhz, you can use bit rates of 921.6k bps under uart error of 1.69%. loop-back mode the S3C24A0 uart provides a test mode referred to as the loopback mode, to aid in isolating faults in the communication link. in this mode, the transmitted data is i mmediately received. this f eature allows the processor to verify the internal transmit and to receive the data path of each sio channel. this mode can be selected by setting the loopback-bit in the ua rt control register (uconn). break condition the break is defined as a continuous low level signal for one frame transmission time on the transmit data output.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-8 ir (infrared) mode the S3C24A0 uart block supports infrared (ir) trans mission and reception, which can be selected by setting the infrared-mode bit in the uart line control register (ulconn). the implementation of the mode is shown in figure 11-3. in ir transmit mode, the transmit period is pulsed at a rate of 3/16, the normal serial transmit rate (when the transmit data bit is zero); in ir receive mode, the rece iver must detect the 3/16 pulsed period to recognize a zero value (refer to the frame timing diagrams shown in figure 11-5 and 11-6 ). irda tx encoder 0 1 0 1 irda rx decoder txd rxd txd irs rxd re uart block figure 11-3. irda function block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-9 start bit stop bit data bits sio frame 0101001101 figure 11-4. serial i/o frame timing diagram (normal uart) 0 start bit stop bit data bits ir transmit frame bit time pulse width = 3/16 bit frame 00 0 01 1 1 1 1 figure 11-5. infrared transmit mode frame timing diagram 0 start bit stop bit data bits ir receive frame 000 01 1 1 1 1 figure 11-6. infrared receive mode frame timing diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-10 uart special registers uart line control register there are two uart line control registers, ulcon0 and ulcon1 in the uart block. register address r/w description reset value ulcon0 0x44400000 r/w uart channel 0 line control register 0x00 ulcon1 0x44404000 r/w uart channel 1 line control register 0x00 ulconn bit description initial state reserved [7] 0 infrared mode [6] the infrared mode determines whether or not to use the infrared mode. 0 = normal mode operation 1 = infrared tx/rx mode 0 parity mode [5:3] the parity mode specifies how parity generation and checking are to be performed during uart transmit and receive operation. 0xx = no parity 100 = odd parity 101 = even parity 110 = parity forced/checked as 1 111 = parity forced/checked as 0 000 number of stop bit [2] the number of stop bi ts specifies how many stop bits are to be used to signal end-of-frame. 0 = one stop bit per frame 1 = two stop bit per frame 0 word length [1:0] the word length indi cates the number of data bits to be transmitted or received per frame. 00 = 5-bits 01 = 6-bits 10 = 7-bits 11 = 8-bits 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-11 uart control register there are two uart control registers, ucon0 and ucon1 in the uart block. register address r/w description reset value ucon0 0x44400004 r/w uart channel 0 control register 0x00 ucon1 0x44404004 r/w uart channel 1 control register 0x00 uconn bit description initial state clock selection [10] select pclk or uartclk for the uart baud rate. 0=pclk : ubrdivn = (int)(pclk / (bps x 16) ) -1 1= uartclk : ubrdivn = (int)( uartclk / (bps x 16) ) -1 0 tx interrupt type [9] interrupt request type 0 = pulse (interrupt is requested as soon as the tx buffer becomes empty in non-fifo mode or reaches tx fifo trigger level in fifo mode) 1 = level (interrupt is requested wh ile tx buffer is empty in non-fifo mode or reaches tx fifo tr igger level in fifo mode) 0 rx interrupt type [8] interrupt request type 0 = pulse (interrupt is requested the instant rx buffer receives the data in non-fifo mode or reaches rx fifo trigger level in fifo mode) 1 = level (interrupt is requested wh ile rx buffer is receiving data in non-fifo mode or reaches rx fi fo trigger level in fifo mode) 0 rx time out enable [7] enable/disable rx time out interr upt when uart fifo is enabled. the interrupt is a receive interrupt. 0 = disable 1 = enable 0 rx error status interrupt enable [6] this bit enables the uart to generat e an interrupt if overrun error occurs during a receive operation. 0 = do not generate receive error status interrupt 1 = generate receive error status interrupt 0 loop-back mode [5] setting loop-back bit to 1 causes the uart to enter the loop-back mode. this mode is provided for test purposes only. 0 = normal operation 1 = loop-back mode 0 send break signal [4] setting this bit causes the uart to send a break during 1 frame time. this bit is auto-cleared after sending the break signal. 0 = normal transmit 1 = send break signal 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-12 uart control register (continued) transmit mode [3:2] these two bits determine wh ich function is currently able to write tx data to the uart transmit buffer register. 00 = disable 01 = interrupt request or polling mode 10 = dma0 or dma2 request (only for uart0), 11 = dma1 or dma3 request (only for uart1) 00 receive mode [1:0] these two bits determine wh ich function is currently able to read data from uart receive buffer register. 00 = disable 01 = interrupt request or polling mode 10 = dma0 or dma2 request (only for uart0), 11 = dma1 or dma3 request (only for uart1) 00 note : when the uart does not reach the fifo trigger level and does not receive data during 3 word time in dma receive mode with fifo, the rx interrupt will be generated (receive time out), and the users should check the fifo status and read out the rest.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-13 uart fifo control register there are two uart fifo control register s, ufcon0 and ufcon1 in the uart block. register address r/w description reset value ufcon0 0x44400008 r/w uart channel 0 fifo control register 0x0 ufcon1 0x44404008 r/w uart channel 1 fifo control register 0x0 ufconn bit description initial state tx fifo trigger level [7:6] these two bits det ermine the trigger level of transmit fifo. 00 = empty 01 = 16-byte 10 = 32-byte 11 = 48-byte 00 rx fifo trigger level [5:4] these two bits det ermine the trigger level of receive fifo. 00 = 1-byte 01 = 8-byte 10 = 16-byte 11 = 32-byte 00 reserved [3] 0 tx fifo reset [2] this bit is auto-cleared after resetting fifo 0 = normal 1= tx fifo reset 0 rx fifo reset [1] this bit is auto-cleared after resetting fifo 0 = normal 1= rx fifo reset 0 fifo enable [0] 0 = fifo disable 1 = fifo mode 0 note : when the uart does not reach the fifo trigger level and does not receive data during 3 word time in dma receive mode with fifo, the rx interrupt will be generated(receive time out), and the users should check t he fifo status and read out the rest.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-14 uart modem control register there are two uart modem control register s, umcon0 and umcon1, in the uart block. register address r/w description reset value umcon0 0x4440000c r/w uart channel 0 modem control register 0x0 umcon1 0x4440400c r/w uart channel 1 modem control register 0x0 umconn bit description initial state reserved [7:5] these bits must be 0's 00 afc(auto flow control) [4] 0 = disable 1 = enable 0 reserved [3:1] these bits must be 0's 00 request to send [0] if afc bit is enabled, this value will be ignored. in this case the S3C24A0 will control nrts automatically. if afc bit is disabled, nrts mu st be controlled by s/w. 0 = 'h' level(inactivate nrts) 1 = 'l' level(activate nrts) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-15 uart tx/rx status register there are two uart tx/rx status registers, utrstat0 and utrstat1 in the uart block. register address r/w description reset value utrstat0 0x44400010 r uart channel 0 tx/rx status register 0x6 utrstat1 0x44404010 r uart channel 1 tx/rx status register 0x6 utrstatn bit description initial state transmitter empty [2] this bit is automatic ally set to 1 when the transmit buffer register has no valid data to transmit and the transmit shift register is empty. 0 = not empty 1 = transmitter(transmit buffer & shifter register) empty 1 transmit buffer empty [1] this bit is automatic ally set to 1 when transmit buffer register is empty. 0 =the buffer register is not empty 1 = empty (in non-fifo mode, interrupt or dma is requested. in fifo mode, interrupt or dma is requested, when tx fifo trigger level is set to 00(empty)) if the uart uses the fifo, users should check tx fifo count bits and tx fifo full bit in the ufstat register instead of this bit. 1 receive buffer data ready [0] this bit is autom atically set to 1 whenever receive buffer register contains valid data, received over the rxdn port. 0 = empty 1 = the buffer register has a received data (in non-fifo mode, interrupt or dma is requested) if the uart uses the fifo, users should check rx fifo count bits and rx fifo full bit in the ufstat register instead of this bit. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-16 uart error status register there are two uart rx error st atus registers, uerstat0 and uerstat1 in the uart block. register address r/w description reset value uerstat0 0x44400014 r uart channel 0 rx error status register 0x0 uerstat1 0x44404014 r uart channel 1 rx error status register 0x0 uerstatn bit description initial state overrun error [0] this bit is automatica lly set to 1 whenever an overrun error occurs during receive operation. 0 = no overrun error during receive 1 = overrun error(interrupt is requested) 0 note : this bit is automatically cleared to 0 when the uart error status register is read.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-17 uart fifo status register there are two uart fifo status registers, ufstat0 and ufstat1 in the uart block. register address r/w description reset value ufstat0 0x44400018 r uart channel 0 fifo status register 0x0000 ufstat1 0x44404018 r uart channel 1 fifo status register 0x0000 ufstatn bit description initial state reserved [15] 0 tx fifo full [14] this bit is automatic ally set to 1 whenever transmit fifo is full during transmit operation 0 = 0-byte tx fifo data 63-byte 1 = full 0 tx fifo count [13:8] number of data in tx fifo 0 reserved [7] 0 rx fifo full [6] this bit is automatica lly set to 1 whenever receive fifo is full during receive operation 0 = 0-byte rx fifo data 63-byte 1 = full 0 rx fifo count [5:0] number of data in rx fifo 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-18 uart modem status register there are two uart modem status register s, umstat0 and umstat1 in the uart block. register address r/w description reset value umstat0 0x4440001c r uart channel 0 modem status register 0x00 umstat1 0x4440401c r uart channel 1 modem status register 0x00 umstat0 bit description initial state reserved [7:5] 0 dcts [4] delta cts this bit indicates that t he ncts input to S3C24A0 has changed state since the last time it was read by cpu. (refer to figure 11-7) 0 = has not changed 1 = has changed 0 reserved [3:1] 0 clear to send [0] 0 = cts signal is not activated(ncts pin is high) 1 = cts signal is activated(ncts pin is low) 0 ncts dcts read_umstat figure 11-7. ncts and delta cts timing diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor uart 11-19 uart transmit buffer register(holdin g register & fifo register) there are two uart transmit buffer regist ers, utxh0 and utxh1 in the uart block. utxhn has an 8-bit data for transmission data. register address r/w description reset value utxh0 0x44400020 w (by byte) uart channel 0 transmit buffer register - utxh1 0x44404020 w (by byte) uart channel 1 transmit buffer register - utxhn bit description initial state txdatan [7:0] transmit data for uartn - uart receive buffer register (holdi ng register & fifo register) there are two uart receive buffer regist ers, urxh0 and urxh1 in the uart block. urxhn has an 8-bit data for received data. register address r/w description reset value urxh0 0x44400024 r (by byte) uart channel 0 receive buffer register - urxh1 0x44404024 r (by byte) uart channel 1 receive buffer register - urxhn bit description initial state rxdatan [7:0] receive data for uartn - note: when an overrun error occurs, the urxhn must be read. if not, the next received data will also make an overrun error, even though the ove rrun bit of uerstatn had been cleared.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. uart S3C24A0 risc microprocessor 11-20 uart baud rate divisor register there are two uart baud rate divisor register s, ubrdiv0 and ubrdiv1 in the uart block. the value stored in the baud rate divisor register (ubrdi vn), is used to determine the serial tx/rx clock rate (baud rate) as follows: ubrdivn = (int)(pclk / (bps x 16) ) ?1 or ubrdivn = (int)( uartclk / (bps x 16) ) ?1 where the ubrdivn should be from 1 to (2 16 -1) and uartclk should be smaller than pclk. for example, if the baud-rate is 115200 bps and pclk or uartclk is 40 mhz , ubrdivn is: ubrdivn = (int)(40000000 / (115200 x 16) ) -1 = (int)(21.7) -1 = 22 -1 = 21 register address r/w description reset value ubrdiv0 0x44400028 r/w baud rate divisior register 0 - ubrdiv1 0x44404028 r/w baud rate divisior register 1 - ubrdiv n bit description initial state ubrdiv [15:0] baud rate division value ubrdivn >0(if uartclk is used, ubrdivn>=0) -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-1 irda controller(preliminary) overview the samsung irda core is a wireless serial communication controller. supporting two different types of irda speed(mir, fir), this core can transmit ir(infrared) pulses up to 4 mbps speed. to lessen the cpu burden, it has configurable fifo feature. this makes it easy to adjust the internal fifo sizes. a user can program the core by accessing 16 internal registers. when receiving the ir pulses, this core detects three kinds of line errors such as crc-error, phy-error and payload length error. feature 1. irda specification compliant - support irda 1.1 physical layer specification (4mbps, 1.152mpbs and 0.576mbps) 2. supports fifo operation in the mir and fir mode 3. configurable fifo size (16-byte or 64-byte) 4. supports back-to-back transactions 5. supports software in selecting temic-ibm or hp transceiver
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-2 block diagram clk_gen master_control lsr a creg mdr fcr iinterrupt control and payload length store ier icr rxflh rxfll txflh txfll tx fifo control thr plr rx fifo control rbr pll fir mod/demodl mir mod/demodl mux m mclk(48mhz) interrupt, dma irrx irtx hresetn tx fifo ram rx fifo ram irsdb w mod demod mod demod ahb bus figure 12-1. block diagram external interface signals irda_tx : irda tx signal (output) irda_rx : irda rx signal (input) irda_sdbw : irda transceiver control (shutdown, bandwidth) (output)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-3 function description fast-speed infrared ( fir ) mode (irda 1.1) in this fir mode, data communicates at the baud rate speed of 4 mbps. in the data transmission mode, the core encodes the payload data into the 4ppm format and attaches t he preamble, start flag, crc-32, and stop flag on the encoded payload and shifts them out serially. in data receive mode, the core works in reverse direction. first, when ir pulse is detected, the core recovers receiver clock from the incoming data and removes the preamble and start flag, then it extracts the payload from the received 4ppm data until it meet s the stop flag. the core detects three different kinds of errors which may occur in the middle of transmission. thes e are the phy-error, the frame-length error and the crc error. the last one, crc error is checked when the entire payload data is received. the micro-controller can monitor the error status of the received frame by reading the line stat us register(lsr) at the end of the frame receiving. the below diagram shows the frame structure of the fir data fr ame. (the specific information of the each field can be found in irda specification.) preamble start flag link layer frame(payload) crc32 stop flag preamble : 1000, 0000, 1010, 1000 start flag : 0000, 1100, 0000, 1100, 0110, 0000, 0110,0000 stop flag : 0000,1100, 0000, 1100, 0000, 0110, 0000, 0110 by programming the internal registers, the number of preambles can be selected from 4 to 32. * note : 4 ppm coding data bit pair(dbp) 4ppm data symbol(dd) 00 1000 01 0100 10 0010 11 0001
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-4 tx enable preamble transmit start flag transmit pay load transmit & crc crc transmit stop flag transmit ~ena ena pre_end str_end pay_end crc_end stp_end & ena apeend frame data with error crc abort by underrun ~abort 2u pulse transmit sip pul_end & ena 0 1 2 3 4 5 6 7 stp_end & ~ena pul_end & ~ena figure 12-2. fir modulation process figure 12-2 shows the fir modulation state machine. the fir transmission mode can be selected by programming acr register. if an underrun condition occurs, the state machine appends the payload with error crc data and terminate the transmission.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-5 rx enable preamble & start flag detect pay load detect & 4ppm decod crc decoding for syndrom ena & prebyte pay_end = last_byte stp_start 0 1 3 4 5 stp_end & ena stp_end & ~ena str_end ~(ena & prebyte) pay load detect & crc check 2 phy_err crc_decod_start stop flag detect figure 12-3. fir demodulation process figure 12-3 shows fir demodulation state machine. the state machine starts when acr register bit 6 is set to logic high. the incoming data will be depa cketized by removing preamble and start flag and stop flag . also, 4ppm decoding and crc decoding is carried out.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-6 medium-speed infrared ( mir ) mode (irda 1.1) in mir mode, data communicates at the speed of 1.152mbps, and 0.576mbps(half mode). the payload data is wrapped around by start flags, crc-16, and st op flags. the start flag should be at least two bytes. both in transmitting and receiving process, the basic wrapping and de-wrapping processes are same as the fir mode, but, the mir mode needs the bit-stuffing procedure. bit stuffing in mir mode have the core insert zero bit per every 5 consecutive ones in transmission mode. in receiving mode, the stuffed bit should be removed. like the fir mode case, three different kind of errors (crc, phy and frame length error ) can be reported to the microcontroller in receiving mode by reading the lsr register. the diagram below shows the data structure of mir frame. sta sta link layer frame (payload) crc16 sto sta : beginning flag, 01111110 binary crc16 : ccitt 16 bit crc sto : ending flag, 01111110 binary the mir pulse is modulated by 1/4 pulse format. the below diagram shows how the pulse is generated. 1.152m mir pulse nrz data figure 12-4. pulse modulation in mir mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-7 tx enable a creg[7] 1st start flag transmit pay load transmit with stuff bit crc transmit with stuff bit stop flag transmit ~ena ena pay_end crc_end stp_end & ena append frame data with erro r crc & eflag abort by underrun ~abort 2u pulse transmit sip pul_end & ena 0 stp_end & ~ena pul_end & ~ena 1 2 3 45 6 str_end figure 12-5. mir modulation process. figure 12-5 shows mir modulation state machine. this machine works very similarly with fir modulation state machine. the major difference is that the mir data transmission needs bit stuffing. after the every 5 consecutive ones, a zero data should be stuffed in mir payload data. the state machine for this bit-stuffing is not presented here.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-8 rx enable str flag detect pay load detect & de-stuff ena & flagbyte 0 1 3 str_end ~(ena&flagbyte) crc check & stp det 2 pay_end stp_end figure 12-6 mir demodulation process figure 12-6 shows the mir demodulation state machine. basically, it has similar structure with fir demodulation state machine. but, instead having 4 ppm demodulation phase, it has the stage of removing stuffed bits from payload data stream. since the mir data stream doesn?t have preamble data, the preamble/start flag data detection stage in mir demodulation is simplified to start flag detection state.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-9 core initialization procedure mir/fir mode initialization operation 1) program the mdr register to select the mir/fir mode. 2) program the acr register to select the transceiver type. - for the temic-ibm type transceiver, program twice in acr[0] = 1?b0 and acr[0] = 1?b1. - for the hp type transceiver, program just once in acr[0] = 1?b0 to fir/mir mode. 3) program the plr register to select the number of preamble or start flag, and tx threshold level. 4) program the rxfll and rxflh register (maximum available receive bytes in frame). 5) program the txfll and txflh register (transmit bytes in transmission frame). 6) program the fcr register (fifo size and rx threshold level). 7) program the ier register ( the types of interrupt). 8) program the acr register (tx enable or rx enable). 9) program the icr register (interrupt enable). 10) service interrupt signal from the core. yes start setup int service parameters int active ? initialize core enable int isr no figure 12-8 general program flowchart
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-10 special function registers irda control register(irda_cnt) register address r/w description reset value irda _cnt 0x41800000 r/w irda control register 0x00 irda _cnt bit description initial state tx enable [7] tx enable. bit 7 must be set to ?1? to enable data transmission in mir/fir ir modes. 0 rx enable [6] rx enable. bit 6 must be set to ?1? to enable data receive in all mir/fir ir modes. 0 core loop [5] core loop for software debugging. the irrx port connects directly to the irtx internally. 0 mir half mode [4] mir half mode. when bit 4 is set to a ?1?, the operating speed in the mir mode changes from 1.152 mbps to 0.576 mbps. 0 send ir pulse [3] send 1.6-us ir pulse. when the irda_mdr[3] bit equals to a ?1? and the cpu writes a ?1? to this bit, the transmitting interface device sends a 1.6-us ir pulse at the end of the frame. bit 3 is cleared automatically by the transmitting interface device at the end of 1.6-us ir pulse data transmission. 0 reserved [2] reserved 0 frame abort [1] frame abort. the cpu can intentionally abort data transmission of a frame by writing a ?1? to bit 1. neither the end flag nor the crc bits are appended to the frame. the receiver will find the frame with the abort pattern in the mir mode and a phy-error in the fir mode. the cpu must reset the tx fifo and reset this bit by writing a ?0? to bit ?1? before next frame can be transmitted. 0 sd/bw [0] this signal controls irda_sdbw output signal. it is used for controlling mode (shutdown, band width) of irda transceiver. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-11 irda mode definition register(irda_mdr) register address r/w description reset value irda_mdr 0x41800004 r/w irda mode definition register 0x00 irda _mdr bit description initial state reserved [7:5] reserved 0 sip select [4] sip select method. if this bit is set to ?1? and the irda_cnt[3] is set to ?1?, the sip pulse is appended at the end of fir/mir tx frame. likewise, when this bit is set to a ?0?, sip is generated at the end of the every fir/mir frames. if irda_cnt[3] is set to ?0?, setting this bit to ?1? doesn?t help to generate sip. along with irda_cnt[3] bit, the way of sip generation can be controlled. 0 temic select [3] bit 3 is temic transceiver select bit. when bit 3 is clear to ?0?, core automatically selects in temic transceiver mode. 0 mode select [2:0] bit 2, bit 1 and bit 0 select the mode of operation as 100 : fir mode 010 : mir mode 0 irda interrupt / dma configuration register(irda_cnf) register address r/w description reset value irda_cnf 0x41800008 r/w irda interrupt / dma configuration register 0x00 irda _cnf bit description initial state reserved [7:4] reserved - dma enable [3] 1 : dma enable 0 dma mode [2] 0 : tx dma 1 : rx dma 0 reserved [1] reserved - interrupt enable [0] the bit 0 enables interrupt output signal. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-12 irda interupt enalble register(irda_ier) register address r/w description reset value irda _ier 0x4180000c r/w irda interrupt enable register 0x00 irda_ier bit description initial state last byte to rx fifo [7] enables state indication interrupt when last byte write to rx fifo. 0 error indication [6] enables error status indication interrupt in data receiving mode. 0 tx underrun [5] enables transmitter under-run interrupt. 0 last byte detect [4] detect stop-flag interrupt enable. if this bit is set to ?1?, an interrupt signal will be activated when the last byte of the received data frame comes into the demodulation block and the crc decoding is finished. 0 rx overrun [3] enables receiver over-run interrupt. 0 last byte read from rx fifo [2] bit 2 enables last byte from rx fifo interrupt which is generated when the microcontroller reads the last byte of the frame from the rx fifo. 0 tx fifo below threshold [1] bit 1 enables an tx fifo below threshold level interrupt when the available empty space in tx fifo is over the threshold level. 0 rx fifo over threshold [0] bit 0 enables received data in rx fifo over threshold level interrupt when the rx fifo is equal to or above the threshold level. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-13 irda interupt identification register(irda_iir) register address r/w description reset value irda _iir 0x41800010 r irda interrupt identification register 0x00 irda _iir bit description initial state last byte to rx fifo [7] last byte write to rx fifo interrupt pending. when the last payload byte of the frame is loaded into the rx fifo, bit 7 is set to ?1?. bit 7 is set prior to bit 2. bit 7 is cleared when it is read. 0 error indication [6] receiver line error indication. bit 6 is set to a ?1? if one of three possible errors occurs in the rx process. with the corresponding interrupt enable bit active, one of phy, crc and frame length errors let this bit go active. bit 6 is cleared when the source of the error is cleared. 0 tx underrun [5] transmit under-run interrupt pending. when corresponding interrupt enable bit is active, bit 5 is set to ?1? if an under-run occurs in tx fifo. bit 5 is cleared by serving the under-run. 0 last byte detect [4] detects last byte of a frame interrupt pending. if the corresponding interrupt enable bit is active, bit 4 is set to ?1? when the demodulation block detects the last byte of a received frame and the crc decoding is finished. bit 4 is cleared when it is read. 0 rx overrun [3] rx fifo over-run interrupt. when corresponding interrupt enable bit is set, bit3 is active, bit 3 is set to ?1? when an overrun occurs in the rx fifo. bit 3 is cleared by serving the over-run. 0 last byte read from rx fifo [2] rx fifo last byte read interrupt. when corresponding interrupt enable bit is active, it is set to ?1? when the cpu reads the last byte of a frame from the rx fifo. it is cleared when it is read. 0 tx fifo below threshold [1] tx fifo below threshold interrupt pending. bit 1 is set to ?1? when the transmitter fifo level is below its threshold level. 0 rx fifo over threshold [0] rx fifo over threshold interrupt pending. bit 0 is set to ?1? when the receiver fifo level is equal to or above its threshold level. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-14 irda line status register(irda_lsr) register address r/w description reset value irda _lsr 0x41800014 r irda line status register 0x03 irda_lsr bit description initial state tx empty [7] transmitter empty. this bit is set to ?1? when tx fifo is empty and the transmitter front-end is idle. 1 reserved [6] reserved 0 received last byte from rx fifo [5] last byte received from rx fifo. it is set to a ?1? when the microcontroller reads the last byte of a frame from the rx fifo and cleared when the mcu reads the irda_lsr register. 0 frame length error [4] frame length error. it is set to ?1? when a frame exceeding the maximum frame length predefined by irda_rxfll and irda_rxflh register is received. this bit is cleared when the microcontroller reads the irda_lsr register. when this error is detected, current frame reception is terminated. data receiving is stopped until the next bof is detected. bit 4 is cleared to ?0? when the irda_lsr register is read by the microcontroller. 0 phy error [3] phy error. in fir mode, it is set to a ?1? when an illegal 4ppm symbol is received. in irda_mir mode, if an abort pattern(more than 7 consecutive ?1?s) is received during reception, this bit is set to ?1?. it is cleared when microcontroller reads the lsr register. 0 crc error [2] crc error. bit 2 is set to ?1? when a bad irda_crc is detected on data receive. it is cleared to ?0? when microcontroller reads the lsr register. 0 reserved [1] reserved 1 rx fifo empty [0] rx fifo empty. it indicates that the rx fifo is empty. when the state of rx fifo turns into empty, it is set to ?1?. when the rx fifo is not empty, it is set to ?0?. 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-15 irda fifo control register(irda_fcr) register address r/w description reset value irda _fcr 0x41800018 r/w irda fifo control register 0x00 irda _fcr bit description initial state rx fifo trigger level select [7:6] receiver fifo trigger level selection. bit 7 bit 6 16-byte rx fifo 64-byte rx fifo 0 0 01 01 0 1 04 16 1 0 08 32 1 1 14 56 00 fifo size select [5] when set to ?1?, 64 bytes tx and rx fifo are selected. when set to ?0?, 16 bytes tx and rx fifo are selected. 0 tx fifo clear notification [4] this bit will be activated when the fifo clear is over. this bit is cleared by the cpu reads this register. 0 rx fifo clear notification [3] this bit will be activated when the fifo clear is over. this bit is cleared by the cpu reads this register. 0 tx fifo reset [2] tx fifo reset. when set to ?1?, bit 2 clears all bytes in the transmitter fifo and reset its counter to ?0?. a ?1? written to bit 2 is self-clearing. 0 rx fifo reset [1] rx fifo reset. when set to ?1?, bit 1 clears all bytes in the receiver fifo and reset its counter to ?0?. a ?1? written to bit 1 is self clearing. 0 fifo enable [0] fifo enable. when set to ?1?, bit 0 enables both the transmitter and receiver fifos. bit 0 must be a ?1? when setting other irda_fcr bits. changing bit 0 clears the fifo. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-16 irda preamble length register(irda_plr) register address r/w description reset value irda _plr 0x4180001c r/w irda preamble length register 0x12 reg_plr bit description initial state preamble length in fir mode [7:6] these two bits decide preamble length to be transmitted at the beginning of each frame in fir mode. the default value of plr[7:6] = ?00? which is equal to 16 preambles. 00 : 16 01 : 4 01: 8 11: 32 00 tx fifo trigger level select [5:4] transceiver fifo trigger level selection. bit 5 bit 4 16-byte fifo 64-byte fifo 00 reserved 0 1 12 48 1 0 08 32 1 1 02 08 note: tx trigger level value means how many data are empty. 01 number of start flags in mir mode [3:0] number of start flags in mir mode. the number of start flags to be transmitted at the beginning of a frame is equal to the irda_plr [3:0] value. the minimum value is 2 . 0010 irda receiver & transmitter buffer register(irda_rbr) register address r/w description reset value irda_rbr 0x41800020 r/w irda receiver & transmitter buffer register 0x00 irda _rbr bit description initial state rx/tx data [7:0] received data (when read data) data to transmit (when write data) 0x00 irda total number of data bytes remained in tx fifo(irda_txno) register address r/w description reset value irda _txno 0x41800024 r the total number of data bytes remained in tx fifo 0x00 irda _txno bit description initial state
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor irda controller 12-17 tx data total number [7:0] the total number of data bytes remained in tx fifo 0x00 irda total number of data bytes remained in rx fifo(irda_rxno) register address r/w description reset value irda _rxno 0x41800028 r the total number of data bytes remained in rx fifo 0x00 irda _rxno bit description initial state rx data total number [7:0] the total number of data bytes remained in rx fifo. 00 irda transmit frame-length register low(irda_txfll) register address r/w description reset value irda _txfll 0x4180002c r/w irda transmit frame-length register low 0x00 irda _txfll bit description initial state tx frame length low [7:0] txfll stores the lower 8 bits of the byte number of the frame to be transmitted . 00 irda transmit frame-length register high(irda_txflh) register address r/w description reset value irda _txflh 0x41800030 r/w irda transmit frame-length register high 0x00 irda _txflh bit description initial state tx frame length high [7:0] txflh stores the upper 8 bits of the byte number of the frame to be transmitted. 00 irda receiver frame-length register low(irda_rxfll) register address r/w description reset value irda _rxfll 0x41800034 r/w irda receive frame-length register low 0x00 irda _rxfll bit description initial state rx frame length low [7:0] rxfll stores the lower 8 bits of the maximum byte number of the frame to be received. 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. irda controller S3C24A0 risc microprocessor 12-18 irda receiver frame-length register high(irda_rxflh) register address r/w description reset value irda _rxflh 0x41800038 r/w irda receive frame-length register high 0x00 irda _rxflh bit description initial state rx frame length high [5:0] txfll stores the upper 6 bits of the maximum byte number of the frame to be received. 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-1 iic-bus interface(preliminary) overview the S3C24A0 risc microprocessor can support a multi-mast er iic-bus serial interface. a dedicated serial data line(sda) and a serial clock line (scl) carry informat ion between bus masters and peripheral devices which are connected to the iic-bus. the sda and scl lines are bi-directional. in multi-master iic-bus mode, multiple S3C24A0 risc mi croprocessors can receive or transmit serial data to or from slave devices. the master S3C24A0, which can initia te a data transfer over the iic-bus, is responsible for terminating the transfer. standard bus arbitration procedure is used in this iic-bus in S3C24A0. to control multi-master iic-bus operations, values must be written to the following registers: ? multi-master iic-bus control register, iiccon ? multi-master iic-bus contro l/status register, iicstat ? multi-master iic-bus tx/rx data shift register, iicds ? multi-master iic-bus address register, iicadd ? multi-master iic-bus sdao ut delay register, sdadly when the iic-bus is free, the sda and scl lines should be both at high level. a high-to-low transition of sda can initiate a start condition. a low-to-high transition of sda can initiate a stop condition while scl remains steady at high level. the start and stop conditions can always be generated by t he master devices. a 7-bit address value in the first data byte, which is put onto the bus after the st art condition has been initiated, can determine the s lave device which the bus master device has selected. the 8 th bit determines the direction of the transfer (read or write). every data byte put onto the sda line should total eight bi ts. the number of bytes which can be sent or received during the bus transfer operation is unlimited. data is alwa ys sent from most-signific ant bit (msb) first, and every byte should be immediately followed by an acknowledge (ack) bit.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-2 pclk address register sda 4-bit prescaler iic-bus control logic iicstat iiccon comparator shift register shift register (iicds) data bus scl figure 13-1. iic-bus block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-3 the iic-bus interface the S3C24A0 iic-bus interface has four operation modes: ? master transmitter mode ? master receive mode ? slave transmitter mode ? slave receive mode functional relationships among these operating modes are described below. start and stop conditions when the iic-bus interface is i nactive, it is usually in slave mode. in ot her words, the interface should be in slave mode before detecting a start condition on the sda line.(a start condition can be initiated with a high-to-low transition of the sda line while the clock signal of scl is high) when the interface state is changed to the master mode, a data transfer on the sda line can be initiated and scl signal generated. a start condition can transfer a one-byte serial data ov er the sda line, and a stop condition can terminate the data transfer. a stop condition is a low-to-high transiti on of the sda line while scl is high. start and stop conditions are always generated by the master. the iic- bus is busy when a start c ondition is generated. a few clocks after a stop condition, the iic-bus will be free, again. when a master initiates a start condition, it should s end a slave address to notify t he slave device. the one byte of address field consist of a 7-bit address and a 1-bit tr ansfer direction indicator (that is, write or read). if bit 8 is 0, it indicates a write operation(transmit oper ation); if bit 8 is 1, it indicates a request for data read(receive operation). the master will finish the transfer operation by transmitti ng a stop condition. if the master wants to continue the data transmission to the bus, it should generate another star t condition as well as a slave address. in this way, the read-write operation can be performed in various formats. scl sda sda scl start condition stop condition figure 13-2. start and stop condition
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-4 data transfer format every byte placed on the sda line should be eight bits in length. the number of bytes which can be transmitted per transfer is unlimited. the first byte following a star t condition should have the address field. the address field can be transmitted by the master when the iic-bus is oper ating in master mode. each byte should be followed by an acknowledgement (ack) bit. the msb bit of the serial data and addresses are always sent first. notes: 1. s: start, rs: repeat start, p: stop, a: acknowledge 2. : from master to slave, : from slave to master write mode format with 7-bit addresses "0" (write) data transferred (data + acknowledge) s slave address 7bits r/w a p data(1byte) a read mode format with 7-bit addresses "1" (read) data transferred (data + acknowledge) s slave address 7 bits r/w a p data a write mode format with 10-bit addresses "0" (write) data transferred (data + acknowledge) p data a s slave address 1st 7 bits r/w a slave address 2nd byte a 11110xx read mode format with 10-bit addresses "1" (read) s slave address 1st 7 bits 11110xx r/w a slave address 2nd byte a rs slave address 1st 7 bits a data transferred (data + acknowledge) p data a r/w "1" (read) figure 13-3. iic-bus interface data format
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-5 sda acknowledgement signal from receiver scl s 1 2789 12 9 acknowledgement signal from receiver msb ack byte complete, interrupt within receiver clock line held low while interrupts are serviced figure 13-4. data transfer on the iic-bus ack signal transmission to finish a one-byte transfer operation completely, the receiver should send an ack bit to the transmitter. the ack pulse should occur at the ninth clock of the scl li ne. eight clocks are required for the one-byte data transfer. the master should generate the clock pulse required to transmit the ack bit. the transmitter should release the sda line by making t he sda line high when the ack clock pulse is received. the receiver should also drive the sda line low during th e ack clock pulse so that the sda is low during the high period of the ninth scl pulse. the ack bit transmit function can be enabled or disabled by software (iicstat). however, the ack pulse on the ninth clock of scl is required to complete a one-byte data transfer operation. data output by transmitter data output by receiver scl from master start condition clock pulse for acknowledgment clock to output 9 8 7 s 1 2 figure 13-5. acknowledge on the iic-bus
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-6 read-write operation in the transmitter mode, after the data is transferred, the iic-bus interface will wait unt il iicds(iic-bus data shift register) is written by a new data. unt il the new data is written, the scl li ne will be held low. after the new data is written to iicds register, the scl line will be released. the S3C24A0 should hold the interrupt to identify the completion of current data transfer. a fter the cpu receives the interrupt request, it should write a new data into iicds, again. in the receive mode, after a data is re ceived, the iic-bus interface will wait until iicds register is read. until the new data is read out, the scl line will be held low. after the new data is read out from iicds register, the scl line will be released. the S3C24A0 should hold the interrupt to identify the completion of the new data reception. after the cpu receives the interrupt r equest, it should read the data from iicds. bus arbitration procedures arbitration takes place on the sda line to prevent the c ontention on the bus between two masters. if a master with a sda high level detects another master with a sda active low level, it w ill not initiate a data transfer because the current level on the bus does not correspond to its own. the arbitration procedure will be extended until the sda line turns high. however when the masters simultaneously lower the sda li ne, each master should evaluate whether or not the mastership is allocated to itself. for the purpose of evaluation, each master shoul d detect the address bits. while each master generates the slaver addr ess, it should also detect the address bit on the sda line because the lowering of sda line is stronger than maintaining high on the line. for example, one master generates a low as first address bit, while the other master is maintaining high. in this case, both masters will detect low on the bus because low is stronger than high even if first master is trying to maintain high on the line. when this happens, low(as the first bit of address) -generating master will get the mastership and high(as the first bit of address) - generating master should withdraw the mastership. if both masters generate low as the first bit of address, there should be an arbitration for second address bit, again. this arbitration will continue to the end of last address bit. abort conditions if a slave receiver can not acknowledge the confirmation of the slave address, it shoul d hold the level of the sda line high. in this case, the master should generate a stop condition and to abort the transfer. if a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by canceling the generation of an ack after the last data byte received from the slave. the slave transmitter should then release the sda to allow a master to generate a stop condition. configuring the iic-bus to control the frequency of the serial clock (scl), t he 4-bit prescaler value can be programmed in the iiccon register. the iic-bus interface address is stored in t he iic-bus address register, iicadd. (by default, the iic-bus interface address is an unknown value.)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-7 flowcharts of the operations in each mode the following steps must be execut ed before any iic tx/rx operations. 1) write own slave address on iicadd register if needed. 2) set iiccon register. a) enable interrupt b) define scl period 3) set iicstat to enable serial output write slave address to iicds write 0xf0(m/t start) to iicstat the data of the iicds is transmitted ack period and then interrupt is pending write 0xd0(m/t stop) to iicstat write new data transmitted to iicds stop? clear pending bit to resume the data of the iicds is shifted to sda start master tx mode has been configured. clear pending bit wait until the stop condition takes effect. end y n figure 13-6 operations for master / transmitter mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-8 write slave address to iicds write 0xb0(m/r start) to iicstat the data of the iicds(slave address) is transmitted ack period and then interrupt is pending write 0x90(m/r stop) to iicstat read a new data from iicds stop? clear pending bit to resume sda is shifted to iicds start master rx mode has been configured. clear pending bit wait until the stop condition takes effect. end y n figure 13-7 operations for master / receiver mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-9 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds(the received slave address) write data to iicds the iic address match interrupt is generated clear pending bit to resume. the data of the iicds is shifted to sda start slave tx mode has been configured. end matched? n y stop? interrupt is pending n y figure 13-8 operations for slave / transmitter mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-10 iic detects start signal. and, iicds receives data. iic compares iicadd and iicds(the received slave address) read data from iicds the iic address match interrupt is generated clear pending bit to resume. sda is shifted to iicds start slave rx mode has been configured. end matched? n y stop? interrupt is pending n y figure 13-9 operations for slave / receiver mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-11 iic-bus interface special registers multi-master iic-bus control register (iiccon) register address r/w description reset value iiccon 0x44600000 r/w iic-bus control register 0x0x iiccon bit description initial state acknowledge generation (1) [7] iic-bus acknowledge enable bit 0 = disable 1 = enable in tx mode, the iicsda is free in the ack time. in rx mode, the iicsda is l in the ack time. 0 tx clock source selection [6] source clock of iic-bus transmit clock prescaler selection bit 0 = iicclk = f pclk /16 1 = iicclk = f pclk /512 0 tx/rx interrupt (5) [5] iic-bus tx/rx interrupt enable/disable bit 0 = disable, 1 = enable 0 interrupt pending flag (2) (3) [4] iic-bus tx/rx interrupt pending flag. writing 1 is impossible. when this bit is read as 1, the iicscl is tied to l and the iic is stopped. to resume the operation, clear this bit as 0. 0 = 1) no interrupt pending(when read), 2) clear pending condition & resume the operation (when write). 1 = 1) interrupt is pending (when read) 2) n/a (when write) 0 transmit clock value (4) [3:0] iic-bus transmit clock prescaler iic-bus transmit clock frequency is determined by this 4-bit prescaler value, according to the following formula: tx clock = iicclk/(iiccon[3:0]+1) undefined notes: 1. interfacing with eeprom, the ack generation may be di sabled before reading the last data in order to generate the stop condition in rx mode. 2. a iic-bus interrupt occurs 1)when a 1-byte transmit or re ceive operation is completed, 2)when a general call or a slave address match occurs, or 3) if bus arbitration fails. 3. to time the setup time of iic sda before iisscl rising edge, iicds has to be written before clearing the iic interrupt pending bit. 4. iicclk is determi ned by iiccon[6]. tx clock can vary by scl transition time. when iiccon[6]=0, iicco n[3:0]=0x0 or 0x1 is not available. 5. if the iicon[5]=0, iicon[4] does not operate correctly. so, it is recommended to set iiccon[4]=1, al though you does not use the iic interrupt.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-12 multi-master iic-bus control/status register (iicstat) register address r/w description reset value iicstat 0x44600004 r/w iic-bus c ontrol/status register 0x0 iicstat bit description initial state mode selection [7:6] iic-bus master /slave tx/rx mode select bits: 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode 00 busy signal status / start stop condition [5] iic-bus busy signal status bit: 0 = read) not busy write) stop signal generate(only for master) 1 = read) busy write) start signal generate(only for master) the data in iicds will be transferred automatically just after the start signal. 0 serial output [4] iic-bus data output enable/disable bit: 0 = disable rx/tx 1 = enable rx/tx 0 arbitration status flag [3] iic-bus arbitration procedure status flag bit: 0 = bus arbitration successful 1 = bus arbitration failed during serial i/o 0 address-as-slave status flag [2] iic-bus address-as-slave status flag bit: 0 = cleared when start/stop condition was detected 1 = received slave address matches the address value in the iicadd. 0 address zero status flag [1] iic-bus address zero status flag bit: 0 = cleared when start/stop condition was detected. 1 = received slave address is 00000000b 0 last-received bit status flag [0] iic-bus last-received bit status flag bit 0 = last-received bit is 0 (ack was received) 1 = last-received bit is 1 (ack was not received) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iic-bus interface 13-13 multi-master iic-bus address register (iicadd) register address r/w description reset value iicadd 0x44600008 r/w iic-bus address register 0xxx iicadd bit description initial state slave address [7:0] 7-bit slave address, latched from the iic-bus : when serial output enable = 0 in the iicstat, iicadd is write-enabled. the iicadd value can be read any time, regardless of the current serial output enable bit (iicstat) setting. slave address = [7:1] not mapped = [0] xxxxxxxx multi-master iic-bus tr ansmit/receive data shift register (iicds) register address r/w description reset value iicds 0x4460000c r/w iic-bus transmit/r eceive data shift register 0xxx iicds bit description initial state data shift [7:0] 8-bit data shift regi ster for iic-bus tx/rx operation : when serial output enable = 1 in the iicstat, iicds is write-enabled. the iicds value can be read any time, regardless of the current serial output enable bit (iicstat) setting xxxxxxxx multi-master iic-bus sdaout delay register (sdadly) register address r/w description reset value sdadly 0x44600010 r/w iic-bus sdaout delay register 0x0 sdadly bit description initial state flten [2] scl & sda line input filter enable 0= disable 1= enable 0 sdadly [1:0] delay setting for iic-bus sda output operation: 00= 0-cycle 01= 5-cycle 10= 10-cycle 11= 15-cycle 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iic-bus interface S3C24A0 risc microprocessor 13-14 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iis-bus interface 14-1 iis-bus interface(preliminary) overview many digital audio systems are introduc ed into the consumer audio market, including compact disc, digital audio tapes, digital sound processors, and digital tv sound. the S3C24A0 iis(inter-ic sound) bus interface can be used to implement a codec interface to an external 8/16-bit stereo audio codec ic for mini-disc and portable applications. it supports the iis bus data format and msb-ju stified data format. iis bus interface provides dma transfer mode for fifo access instead of an interrupt. it can transmit or receive data simultaneously as well as transmit or receive data only. features ? iis, msb-justified format compatible ? 8/16-bit data per channel ? 16, 32, 48fs(sampling frequency) serial bit clock per channel ? 256, 384fs master clock ? programmable frequency divider fo r master clock and codec clock ? 128 bytes(2 x 64) fifo for transmit and receive ? normal and dma transfer mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iis-bus interface S3C24A0 risc microprocessor 14-2 block diagram addr data cntl pclk brfc ipsr_a ipsr_b txfifo rxfifo sclkg chnc sftr lrck sclk sd cdclk figure 14-1. iis-bus block diagram functional descriptions bus interface, register bank, and st ate machine(brfc) - bus interface l ogic and fifo access are controlled by the state machine. 5-bit dual prescaler(ipsr) - one prescaler is used as the ma ster clock generator of t he iis bus interface and the other is used as the exte rnal codec clock generator. 64-byte fifos(txfifo, rxfifo) - in trans mit data transfer, data are written to txfifo, and, in the receive data transfer, data are read from rxfifo. master iisclk generator(sclkg) - in ma ster mode, serial bit clock is generated from the master clock. channel generator and state machi ne(chnc) - iisclk and iislrck are generated and controlled by the channel state machine. 16-bit shift register(sftr) - parallel data is shifted to se rial data output in the trans mit mode, and serial data input is shifted to parallel data in the receive mode. transmit or receive only mode normal transfer iis control register has fifo ready flag bits for transmit and receive fifo. when fifo is ready to transmit data, the fifo ready flag is set to '1 ' if transmit fifo is not empty. if transmit fifo is empty, fifo ready flag is set to '0'. when receive fifo is not full, the fifo ready flag for receive fifo is set to '1' ; it indicate s that fifo is ready to receive data. if receive fifo is full, fifo ready flag is set to '0'. these flags can determine the time that cpu is to write or read fifos. serial data can be transmitted or received while cpu is accessing transmit and receive fifos in this way.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iis-bus interface 14-3 dma transfer in this mode, transmit or receive fi fo access is made by the dma controlle r. dma service request in transmit or receive mode is made by the fi fo ready flag automatically. transmit and receive mode in this mode, iis bus interface can transmit and receive data simultaneously. audio serial interface format iis-bus format the iis bus has four lines, serial dat a input(iisdi), serial dat a output(iisdo), left/right channel select(iislrck), and serial bit clock(iisclk); the device ge nerating iislrck and iisclk is the master. serial data is transmitted in 2's complement with t he msb first. the msb is transmitted first because the transmitter and receiver may have different word lengths. it is not necessary for the transmitter to know how many bits the receiver can handle, nor does the receiver need to know how many bits are being transmitted. when the system word length is greater than the transmitter word length, the word is truncated(least significant data bits are set to '0') for data transmissi on. if the receiver is sent more bits than its word length, the bits after the lsb are ignored. on the other hand, if the receiv er is sent fewer bits than its wo rd length, the missing bits are set to zero internally. and so, the msb has a fixed posit ion, whereas the position of the lsb depends on the word length. the transmitter always sends the msb of the next word at one clock period after the iislrck change. serial data sent by the transmitter may be synchronized with either the trailing (high to low) or the leading (low to high) edge of the clock signal. however, the seri al data must be latched into the receiver on the leading edge of the serial clock signal, and so there are some rest rictions when transmitting data that is synchronized with the leading edge. the lr channel select line indicates the channel being transmitted. iislrck may c hange either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. in the slave, this signal is latched on the leading edge of the clock signal. the iislrck line changes one clock period before the msb is transmitted. this allows the slave transmitter to derive synchronous timi ng of the serial data that will be set up for transmission. furthermore, it enables the receiver to store the previous word and clear the input for the next word. msb(left) justified msb / left justified bus has the same lines as the iis fo rmat. it is only different with the iis bus that transmitter always sends the msb of the nex t word when the iislrck change.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iis-bus interface S3C24A0 risc microprocessor 14-4 iis-bus format (n=8 or 16) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) msb (1st) lrck sclk sd left right left msb-justified format (n=8 or 16) 2nd bit n-1th bit lsb (last) msb (1st) 2nd bit n-1th bit lsb (last) lrck sclk sd left right msb (1st) figure 14-2. iis-bus and msb(left) -justified data interface formats sampling frequency and master clock master clock frequency(pclk) can be selected by sampli ng frequency as shown in table 21-1. because pclk is made by iis prescaler, the prescaler value and pclk type(256 or 384fs) should be det ermined properly. serial bit clock frequency type(16/32/48fs) can be se lected by the serial bit per channel and pclk as shown in table 21-2. table 14-1 codec clock (iiscdclk = 256 or 384fs) iislrck (fs) 8.000 khz 11.025 khz 16.000 khz 22.050 khz 32.000 khz 44.100 khz 48.000 khz 64.000 khz 88.200 khz 96.000 khz 256fs iiscdclk 2.0480 2.8224 4.0960 5.6448 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 (mhz) 384fs 3.0720 4.2336 6.1440 8.4672 12.2880 16.9344 18.4320 24.5760 33.8688 36.8640 table 14-2 usable serial bit clock fr equency (iisclk = 16 or 32 or 48fs) serial bit per channel 8-bit 16-bit serial clock frequency (iisclk) @iiscdclk = 256fs 16fs, 32fs 32fs @iiscdclk = 384fs 16fs, 32fs, 48fs 32fs, 48fs
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iis-bus interface 14-5 iis-bus interface special registers iis control register (iiscon) register address r/w description reset value iiscon 0x44700000 r/w iis control register 0x100 iiscon bit description initial state left/right channel index (read only) [8] 0 = left 1 = right 1 transmit fifo ready flag (read only) [7] 0 = empty 1 = not empty 0 receive fifo ready flag (read only) [6] 0 = full 1 = not full 0 transmit dma service request [5] 0 = disable 1 = enable 0 receive dma service request [4] 0 = disable 1 = enable 0 transmit channel idle command [3] in idle st ate the iislrck is inactive(pause tx) 0 = not idle 1 = idle 0 receive channel idle command [2] in idle state the iislrck is inactive(pause rx) 0 = not idle 1 = idle 0 iis prescaler [1] 0 = disable 1 = enable 0 iis interface [0] 0 = disable (stop) 1 = enable (start) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iis-bus interface S3C24A0 risc microprocessor 14-6 iis mode register (iismod) register address r/w description reset value iismod 0x44700004 r/w iis mode register 0x0 iismod bit description initial state master/slave mode select [8] 0 = master mode (iislrck and iisclk are output mode) 1 = slave mode (iislrck and iisclk are input mode) 0 transmit/receive mode select [7:6] 00 = no transfer 01 = receive mode 10 = transmit mode 11 = transmit and receive mode 00 active level of left/right channel [5] 0 = low for left channel (high for right channel) 1 = high for left channel (low for right channel) 0 serial interface format [4] 0 = iis compatible format 1 = msb(left)-justified format 0 serial data bit per channel [3] 0 = 8-bit 1 = 16-bit 0 master clock frequency select [2] 0 = 256fs 1 = 384fs (fs : sampling frequency) 0 serial bit clock frequency select [1:0] 00 = 16fs 01 = 32fs 10 = 48fs 11 = n/a 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor iis-bus interface 14-7 iis prescaler register (iispsr) register address r/w description reset value iispsr 0x44700008 r/w iis prescaler register 0x0 iispsr bit description initial state prescaler control a [9:5] data value : 0 ~ 31 note : prescaler a makes the master clock that is used the internal block and division factor is n+1. 00000 prescaler control b [4:0] data value : 0 ~ 31 note : prescaler b makes the master clock that is used the external block and division factor is n+1. 00000 iis fifo control register (iisfcon) register address r/w description reset value iisfcon 0x4470000c r/w iis fifo interface register 0x0 iisfcon bit description initial state transmit fifo access mode select [15] 0 = normal 1 = dma 0 receive fifo access mode select [14] 0 = normal 1 = dma 0 transmit fifo [13] 0 = disable 1 = enable 0 receive fifo [12] 0 = disable 1 = enable 0 transmit fifo data count (read only) [11:6] data count value = 0 ~ 32 000000 receive fifo data count (read only) [5:0] data count value = 0 ~ 32 000000 iis fifo register (iisfifo) iis bus interface contains two 64-byte fifo for the transmit and receive mode. each fifo has 16-width and 32- depth form, which allows the fifo to handles data by halfword unit regardl ess of valid data size. transmit and receive fifo access is performed through fi fo entry; the address of fentry is 0x44700010 register address r/w description reset value iisfifo 0x44700010 r/w iis fifo register 0x0 iisfifo bit description initial state fentry [15:0] transmit/receive data for iis 0x0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. iis-bus interface S3C24A0 risc microprocessor 14-8
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor spi interface 15-1 spi interface (preliminary) overview the S3C24A0 serial peripheral interface(spi) can interface the serial data transfer. there are two spi in S3C24A0 and each spi has two 8bit shift register for transmission and receiving, respectively. during an spi transfer, data is simultaneously transmitted (shifted out serially) and receiv ed (shifted in serially) 8bit serial data at a frequency determined by its corresponding control register settings. if you want only to transmit, you may treat the received data as dummy. otherwise, if you want only to receive, you should transmit dummy '1' data. there are 4 i/o pin signals associated with spi transfers: the sck, the miso data line, the mosi data line, and the active low /ss pin(input). features ? spi protocol(ver 2.11) compatible ? 8-bit shift register for transmit ? 8-bit shift register for receive ? 8-bit prescaler logic ? polling, interrupt, and dma transfer mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. spi interface S3C24A0 risc microprocessor 15-2 block diagram 8bit prescaler 1 pclk status register 1 prescaler register 1 /ss nss 0 sck spiclk 0 mosi spimosi 0 miso spimiso 0 pin control logic 0 mstr tx 8bit shift reg 0 rx 8bit shift reg 0 lsb msb lsb msb 8 8 clock spi clock (master) cpol cpha clock logic 0 mulf dcol redy apb i/f 0 (int dma 0) master slave slave master slave slave master data bus int 0 / int 1 req0 / req1 ack0 / ack1 /ss nss 1 sck spiclk 1 mosi spimosi 1 miso spimiso 1 pin control logic 1 mstr tx 8bit shift reg 1 rx 8bit shift reg 1 lsb msb lsb msb 8 8 clock spi clock (master) cpol cpha clock logic 1 mulf dcol redy apb i/f 1 (int dma 1) master slave slave master slave slave master int 0 / int 1 req0 / req1 ack0 / ack1 8bit prescaler 0 pclk status register 0 prescaler register 0 figure 15-1. spi block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor spi interface 15-3 spi operation using the spi interface, 8-bit data can be sending and re ceiving data simultaneously with an external device. a serial clock line synchronizes shifting and sampling of the information on the two serial data lines. when spi is the master, transmission frequency can be controlled by setti ng the appropriate bit to sppren register. you can modify its frequency to adjust the baud rate data register va lue. when spi is a slave, other master supplies the clock. when a programmer writes byte data to sptdatn register, spi transmit and receive operation will start simultaneously. in some cases, nss should be ac tivated before writing byte data to sptdatn. programming procedure when a byte data is written into the sptdatn register , spi starts to transmit if ensck and mstr of spconn register are set. there is a typical programming procedure to operate an spi card. to program the spi modules, follow these basic steps : 1. set baud rate prescaler register(sppren) 2. set spconn to configure properly the spi module 3. write data 0xff to sptdatn 10 times in order to initialize mmc or sd card 4. set a gpio pin, which acts as nss, to low to activate the mmc or sd card. 5. tx data check the status of transfer ready flag (redy=1), and then write data to sptdatn. 6. rx data(1) : spconn's tagd bit disable = normal mode write 0xff to sptdatn, then confirm redy to set, and then read data from read buffer 7. rx data(2) : spconn's tagd bit enable = tx auto garbage data mode confirm redy to set, and then read data from read buffer(then automatically start to transfer) 8. set a gpio pin, which acts as nss, to high, to deactivate mmc or sd card.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. spi interface S3C24A0 risc microprocessor 15-4 spi transfer format S3C24A0 supports 4 different format to transfer the data. four waveforms are shown for spiclk. * lsb of previously transmitted character cycle mosi 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 lsb spiclk miso msb cpol = 1, cpha = 1 (format b) * msb of character just received cycle mosi 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 lsb msb * spiclk miso msb cpol = 1, cpha = 0 (format a) cycle mosi 1 2 3 4 5 6 7 8 6 5 4 3 2 1 lsb 6 5 4 3 2 1lsb * spiclk miso *lsb cpol = 0, cpha = 1 (format b) * msb of character just received cycle mosi 1 2 3 4 5 6 7 8 msb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 lsb msb * spiclk miso msb cpol = 0, cpha = 0 (format a) * lsb of previously transmitted character *lsb msb msb figure 15-2. spi transfer format
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor spi interface 15-5 steps for transmit by dma 1. the spi is configured as dma mode. 2. dma is configured properly. 3. the spi requests dma service. 4. dma transmits 1byte data to the spi. 5. the spi transmits the data to card. 6. go to step 3 until dma count is 0. 7. the spi is configured as interrupt or polling mode with smod bits. steps for receive by dma 1. the spi is configured as dma start with smod bits and setting tagd bit. 2. dma is configured properly. 3. the spi receives 1byte data from card. 4. the spi requests dma service. 5. dma receives the data from the spi. 6. write data 0xff automatically to sptdatn. 7. go to step 4 until dma count is 0. 8. the spi is configured as polling mode with smod bits and clearing tagd bit. 9. if spstan?s redy flag is set, then read the last byte data. note: total received data = dma tc values + the last data in polling mode(step 9). first dma received data is dummy, so user can neglect that.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. spi interface S3C24A0 risc microprocessor 15-6 spi special registers spi control register register address r/w description reset value spcon0 0x44500000 r/w spi channel 0 control register 0x00 spcon1 0x44500020 r/w spi channel 1 control register 0x00 spconn bit description initial state spi mode select (smod) [6:5] determines how and by what sptdat is read/written 00 = polling mode, 01 = interrupt mode 10 = dma mode, 11 = reserved 00 sck enable (ensck) [4] determines what you want sck enable or not(only master) 0 = disable, 1 = enable 0 master/slave select(mstr) [3] determines what mode you want master or slave 0 = slave, 1 = master note: in slave mode, there should be set up time for master to initiate tx / rx. 0 clock polarity select(cpol) [2] determines an active high or active low clock. 0 = active high, 1 = active low 0 clock phase select(cpha) [1] this bit selects one of two fundamentally different transfer formats. 0 = format a, 1 = format b 0 tx auto garbage data mode enable (tagd) [0] this bit decides whether the receiving data only needs or not. 0 = normal mode, 1 = tx auto garbage data mode note: in normal mode, you only want to receive data, you should transmit dummy 0xff data. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor spi interface 15-7 spi status register register address r/w description reset value spsta0 0x44500004 r spi channel 0 status register 0x01 spsta1 0x44500024 r spi channel 1 status register 0x01 spstan bit description initial state reserved [7:3] data collision error flag(dcol) [2] this flag is set if the sptdatn is written or the sprdatn is read while a transfer is in progress and cleared by reading the spstan. 0 = not detect, 1 = collision error detect 0 multi master error flag (mulf) [1] this flag is set if the nss signal goes to active low while the spi is configured as a master, and sppinn's enmul bit is multi master errors detect mode. mulf is cleared by reading spstan. 0 = not detect, 1 = multi master error detect 0 transfer ready flag (redy) [0] this bit indicates that sptdatn or sprdatn is ready to transmit or receive. this flag is automatically cleared by writing data to sptdatn. 0 = not ready, 1 = data tx/rx ready 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. spi interface S3C24A0 risc microprocessor 15-8 spi pin control register when the spi system is enabled, the direction of pins is controlled by mstr bit of spconn register except nss pin. the direction of nss pin is input always. when the spi is a master, nss pin is used to check multi- master error, provided the sppin's enmul bit is active, and another gpio should be used to select a slave. if the spi is configured as a slave, nss pin is used to select spi as a slave by one master. register address r/w description reset value sppin0 0x44500008 r/w spi channel 0 pin control register 0x02 sppin1 0x44500028 r/w spi channel 1 pin control register 0x02 sppinn bit description initial state reserved [7:3] multi master error detect enable (enmul) [2] the /ss pin is used as an input to detect multi master error when the spi system is a master. 0 = disable(general purpose), 1 = multi master error detect enable 0 reserved [1] this bit should be ?1?. 1 master out keep(keep) [0] determines mosi drive or release when 1byte transmit finish(only master) 0 = release, 1 = drive the previous level 0 the spimiso(miso) and spimosi(mosi) data pins are used for transmitting and receiving serial data. when the spi is configured as a master, spimiso(miso) is the master data input line, spimosi(mosi) is the master data output line, and spiclk(sck) is the clock output line. when as a slave, these pins reverse roles. in a multiple- master system, all spiclk(sck) pins are tied together, all spimosi(mosi) pins are tied together, and all spimiso(miso) pins are tied together. only an spi master can experience a multi master error, caused when a second spi device becomes a master and selects this device as if it were a slave. when this type error is detected, the following actions are taken immediately. but you must previously set sppinn?s enmul bit if you want to detect this error. 1. the spconn's mstr bit is forced to 0 to operate slave mode. 2. the spstan's mulf flag is set, and an spi interrupt is generated.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor spi interface 15-9 spi baud rate prescaler register register address r/w description reset value sppre0 0x4450000c r/w spi cannel 0 baud rate prescaler register 0x00 sppre1 0x4450002c r/w spi cannel 1 baud rate prescaler register 0x00 sppren bit description initial state prescaler value [7:0] determines spi clock rate as above equation. baud rate = pclk / 2 / (prescaler value + 1) 0x00 note : baud rate should be less than 25mhz. spi tx data register register address r/w description reset value sptdat0 0x44500010 r/w spi channel 0 tx data register 0x00 sptdat1 0x44500030 r/w spi channel 1 tx data register 0x00 sptdatn bit description initial state tx data register [7:0] this field contains t he data to be transmitted over the spi channel 0x00 spi rx data register register address r/w description reset value sprdat0 0x44500014 r spi channel 0 rx data register 0x00 sprdat1 0x44500034 r spi channel 1 rx data register 0x00 sprdatn bit description initial state rx data register [7:0] this field contains the data to be received over the spi channel 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. spi interface S3C24A0 risc microprocessor 15-10 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-1 ac97 controller overview the ac97 controller unit of S3C24A0 supports the ac97 revision 2.0 features. ac97 controller communicates with ac97 codec using audio controller link (ac-link). controller sends the stereo pcm data to codec. the external digital-to-analog converter (dac) in the codec then converts the audio sample to an analog audio waveform. also, controller receives the stereo pcm data and the mono mic data from codec then store in memories. this chapter describes the programming model fo r the ac97 controller unit. the information in this chapter requires an understanding of the ac97 revision 2.0 specification. feature _ independent channels for stereo pcm in, stereo pcm out, mono mic in. _ 32bit (16-bit x 2), 16 entries for stereo pcm in, stereo pcm out and 16bit, 16 entries for mic in. _ all of the channels support only 16-bit sample lengths. _ variable sampling rate ac97 codec interface (48khz and below) _ dma-based operation and interrupt based operation. _ only primary codec support.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-2 ac97 controller operation block diagram figure 16-1 shows the functional block diagram of s3c 24a0 ac97 controller. the ac97 signals form the ac-link, which is a point-to-point synchronous serial interconnection that supports full-duplex data transfers. all digital audio streams and command/status information are communicated over the ac-link. apb i/f dma engine interrupt control mic in fifo pcm out fifo pcm in fifo sfr ac-link i/f fsm & control apb ac-link figure 16-1 ac97 block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-3 internal data path figure 16-2 shows the internal data path of s3c 24a0 ac97 controller. it has stereo pulse code modulated (pcm) in, stereo pcm out and mono mic-in buffers, which consist of 16-bit, 16 entries buffer. also it has 20-bit i/o shift register via ac-link. command addr register command data register pcm out buffer (regfile 16 bit x 2 x 16 entry) pwdata response data register mic in buffer (regfile 16 bit x16 entry) pcm in buffer (regfile 16 bit x 2 x 16 entry) prdata input shift register (20 bit) output shift register (20 bit) sdata_in sdata_out figure 16-2. internal data path
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-4 operation flow chart system reset or cold reset set gpio and release intmsk/subintmsk bits enable codec ready interrupt codec ready interrupt ? time out condition ? disable codec ready interrupt dma operation or pio (interrupt or polling) operation yes no controller off no figure 16-3. ac97 operation flow chart
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-5 ac-link digital interface protocol each ac97 codec incorporates a five-pin digital serial in terface that links it to the S3C24A0 ac97 controller. ac- link is a full-duplex, fixed-clock, pcm digital stream. it employs a time division multiplexed (tdm) scheme to handle control register accesses and multiple input and out put audio streams. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams. each stream has 20-bit sample resolution and requires a dac and an analog-to-digital converter (adc) with a minimum 16-bit resolution. sync sdata_out sdata_in slot # (256-bit) tag cmd addr cmd data pcm l front pcm r front tag status addr pcm mic status data pcm left pcm right rsrvd rsrvd rsrvd 0123456789101112 16-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit 20-bit rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd rsrvd figure 16-4. bi-directional ac-link frame with slot assignments figure 28-4 shows tag and data phase organization for the controller and the codec. the figure also lists the slot definitions that the S3C24A0 ac97 controller supports. the S3C24A0 ac97 controller provides synchronization for all data transaction on the ac-link.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-6 a data transaction is made up of 256 bits of information broken up into groups of 13 time slots and is called a frame. time slot 0 is called the tag phase and is 16 bits long. the other 12 time slots are called the data phase. the tag phase contains one bit that identifies a valid frame and 12 bits that identify the time slots in the data phase that contain valid data. each time slot in the data phase is 20 bits long. a frame begins when sync goes high. the amount of time that sync is high corresponds to the tag phase. ac97 frames occur at fixed 48 khz intervals and are synchronous to the 12.288 mhz bit rate clock, bitclk. the controller and the codec use the sync and bitclk to determine when to send transmit data and when to sample received data. a transmitter transitions the serial data stream on each rising edge of bitclk and a receiver samples the serial data stream on falling edges of bitclk. the transmitter must tag the valid slots in its serial data stream. the valid slots are tagged in slot 0. serial data on the ac-link is ordered most significant bit (msb) to least significant bit (lsb). the tag phase?s first bit is bit 15 and the first bit of each slot in data phase is bit 19. the last bit in any slot is bit 0. ac-link output frame (sdata_out) sdata_out bit_clk sync ac '97 samples sync assertion here ac '97 controller samples first sdata_out bit of frame here end of previous audio frame valid frame slot(1) slot(2) slot(12) "0" id1 id0 19 0 tag phase data phase 19 0 start of data phase slot# 1 end of data frame slot# 12 48khz 12.288mhz figure 16-5. ac-link output frame
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-7 ac-link input frame (sdata_in) sdata_out bit_clk sync ac '97 samples sync assertion here ac '97 controller samples first sdata_in bit of frame here end of previous audio frame codec ready slot(1) slot(2) slot(12) "0" "0" "0" 19 0 tag phase data phase 19 0 start of data phase slot# 1 end of data frame slot# 12 figure 16-6. ac-link input frame
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-8 ac97 powerdown sdata_out sdata_in bit_clk sync slot 12 prev.frame write to 0x26 slot 12 prev.frame tag tag data pr4 figure 16-7. ac97 powerdown timing powering down the ac-link the ac-link signals enter a low power mode when the ac97 codec powerdown regist er (0x26) bit pr4 is set to a 1 (by writing 0x1000). then the primary codec drives bot h bitclk and sdata_in to a logic low voltage level. the sequence follows the timing diagram shown in figure 16-7. the ac97 controller transmits the write to powerdown register (0x26) over the ac-link. set up the ac97 controller so that it does not transmit data to slots 3-12 when it writes to the powerdown register bit pr4 (data 0x1000), and it does not require the codec to process other data when it receives a power down request. when the codec processes the request it immediately transitions bitclk and sdata_in to a logic low level. the ac97 controller drives sync and sdata_out to a logic lo w level after programming the ac_glbctrl register. waking up the ac-link - wake up triggered by the ac97 controller ac-link protocol provides for a cold ac97 reset and a warm ac97 reset. the current power-down state ultimately dictates which ac97 reset is used. registers must stay in the same state during all power-down modes unless a cold ac97 reset is performed. in a cold ac97 reset, the ac 97 registers are initialized to their default values. after a power down, the ac-link must wait for a minimum of four audio frame times after the frame in which the power down occurred before it can be reactivated by reassert ing the sync signal. when ac-link powers up, it indicates readiness through the codec ready bit (input slot 0, bit 15).
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-9 pr0=1 normal adcs off pr0 dacs off pr1 analog off pr2 or pr3 digital i/f off pr4 shut off ac-link default pr1=1 pr2=1 pr4=1 warm reset pr0=0 & adc=1 pr1=0 & dac=1 pr2=0 & anl=1 cold reset ready=1 figure 16-8 ac97 power down/power up flow cold ac97 reset a cold reset is generated when the nreset pin is asserted through the ac_glbctrl. asserting and deasserting nreset activates bitclk and sdata_out. all ac97 control registers are initialized to their default power on reset values. nreset is an asynchronous ac97 input. warm ac97 reset a warm ac97 reset reactivates the ac-link without altering the current ac97 register values. a warm reset is generated when bitclk is absent and sync is driven high. in normal audio frames, sync is a synchronous ac97 input. when bitclk is absent, sync is treated as an asynchronous input used to generate a warm reset to ac97.the ac97 controller must not activate bitclk until it samples sync low again. this prevents a new audio frame from being falsely detected; when the ac97 controller receives a wake-up from the codec.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-10 ac97 controller special registers ac97 global control register (ac_glbctrl) register address r/w description reset value ac_glbctrl 0x45000000 r/w ac97 global control register 0x000000 ac_glbctrl bit description initial state reserved [31:23] reserved 0x00 codec ready interrupt enable [22] 0 : disable 1 : enable 0 pcm out channel underrun interrupt enable [21] 0 : disable 1 : enable ( fifo is empty) 0 pcm in channel overrun interrupt enable [20] 0 : disable 1 : enable ( fifo is full) 0 mic in channel overrun interrupt enable [19] 0 : disable 1 : enable ( fifo is full) 0 pcm out channel threshold interrupt enable [18] 0 : disable 1 : enable ( fifo is half empty) 0 pcm in channel threshold interrupt enable [17] 0 : disable 1 : enable ( fifo is half full) 0 mic in channel threshold interrupt enable [16] 0 : disable 1 : enable ( fifo is half full) 0 reserved [15:14] reserved 00 pcm out channel transfer mode [13:12] 00 : off 01 : pio 10 : dma 11 : reserved 00 pcm in channel transfer mode [11:10] 00 : off 01 : pio 10 : dma 11 : reserved 00 mic in channel transfer mode [9:8] 00 : off 01 : pio 10 : dma 11 : reserved 00 reserved [7:4] reserved 0000 transfer data enable using ac-link [3] 0 : disable 1 : enable 0 ac-link on [2] 0 : off 1 : sync signal transfer to codec 0 warm reset [1] 0 : normal 1 : wake up codec from power down 0 cold reset [0] 0 : normal 1 : reset codec and controller logic 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-11 ac97 global status register (ac_glbstat) register address r/w description reset value ac_glbstat 0x45000004 r ac97 gl obal status register 0x00000000 ac_glbstat bit description initial state reserved [31:23] reserved 0x00 codec ready interrupt [22] 0 : not requested 1 : requested 0 pcm out channel underrun interrupt [21] 0 : not requested 1 : requested 0 pcm in channel overrun interrupt [20] 0 : not requested 1 : requested 0 mic in channel overrun interrupt [19] 0 : not requested 1 : requested 0 pcm out channel threshold interrupt [18] 0 : not requested 1 : requested 0 pcm in channel threshold interrupt [17] 0 : not requested 1 : requested 0 mic in channel threshold interrupt [16] 0 : not requested 1 : requested 0 reserved [15:3] reserved. 0x000 controller main state [2:0] 000 : idle 001 : init 010 : ready 011 : active 100 : lp 101 : warm 000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-12 ac97 codec command register (ac_codec_cmd) register address r/w description reset value ac_codec_cmd 0x45000008 r/w ac97 codec command register 0x00000000 ac_codec_cmd bit description initial state reserved [31:24] reserved 0x00 read enable [23] 0 : command write 1 : status read 0 address [22:16] codec command address 0x00 data [15:0] codec command data 0x0000 ac97 codec status register (ac_codec_stat) register address r/w description reset value ac_codec_stat 0x4500000c r ac97 codec status register 0x00000000 ac_codec_stat bit description initial state reserved [31:23] reserved. 0x00 address [22:16] codec status address 0x00 data [15:0] codec status data 0x0000 ac97 pcm out/in channel fifo address register (ac_pcmaddr) register address r/w description reset value ac_pcmaddr 0x45000010 r ac97 pcm out/in c hannel fifo address register 0x00000000 ac_pcmaddr bit description initial state reserved [31:28] reserved. 0000 out read address [27:24] pcm out channel fifo read address 0000 reserved [23:20] reserved. 0000 in read address [19:16] pcm in channel fifo read address 0000 reserved [15:12] reserved. 0000 out write address [11:8] pcm out channel fifo write address 0000 reserved [7:4] reserved. 0000 in write address [3:0] pcm in channel fifo write address 0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor ac97 controller 16-13 ac97 mic in channel fifo address register (ac_micaddr) register address r/w description reset value ac_micaddr 0x45000014 r ac97 mic in c hannel fifo address register 0x00000000 ac_micaddr bit description initial state reserved [31:20] reserved. 0000 read address [19:16] mic in channel fifo read address 0000 reserved [15:4] reserved. 0x000 write address [3:0] mic in channel fifo write address 0000 ac97 pcm out/in channel fifo data register (ac_pcmdata) register address r/w description reset value ac_pcmdata 0x45000018 r/w ac97 pcm out/in channel fifo data register 0x00000000 ac_pcmdata bit description initial state left data [31:16] pcm out/in left channel fifo data read : pcm in left channel write : pcm out left channel 0x0000 right data [15:0] pcm out/in right channel fifo data read : pcm in right channel write : pcm out right channel 0x0000 ac97 mic in channel fifo data register (ac_micdata) register address r/w description reset value ac_micdata 0x4500001c r/w ac97 mic in channel fifo data register 0x00000000 ac_micdata bit description initial state reserved [31:16] reserved 0x0000 mono data [15:0] mic in mono channel fifo data 0x0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. ac97 controller S3C24A0 risc microprocessor 16-14 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb host 17-1 usb host controller (preliminary) overview S3C24A0 supports 2 port usb host interface as follows; open hci rev 1.0 compatible. usb rev1.1 compatible 2 down stream ports. support for both lowspeed and highspeed usb devices figure 17-1. usb host controller block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb host S3C24A0 risc microprocessor 17-2 usb host controller special registers the S3C24A0 usb host controller complies with open hci rev 1.0. please refer to open host controller interface rev 1.0 specification for detail information. ohci registers for usb host controller register base address r/w description reset value hcrevision 0x41000000 - - hccontrol 0x41000004 - - hccommonstatus 0x41000008 - - hcinterruptstatus 0x4100000c - - hcinterruptenable 0x41000010 - - hcinterruptdisable 0x41000014 - control and status group - hchcca 0x41000018 - - hcperiodcuttented 0x4100001c - - hccontrolheaded 0x41000020 - - hccontrolcurrented 0x41000024 - - hcbulkheaded 0x41000028 - - hcbulkcurrented 0x4100002c - - hcdonehead 0x41000030 - memory pointer group - hcrminterval 0x41000034 - - hcfmremaining 0x41000038 - - hcfmnumber 0x4100003c - - hcperiodicstart 0x41000040 - - hclsthreshold 0x41000044 - frame counter group - hcrhdescriptora 0x41000048 - - hcrhdescriptorb 0x4100004c - - hcrhstatus 0x41000050 - - hcrhportstatus1 0x41000054 - - hcrhportstatus2 0x41000058 - root hub group -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-1 usb device overview usb device controller is designed to provide a high per formance full speed function controller solution with dma i/f. usb device controller allows bulk transfer with dma, interrupt transfer and control transfer. the functions are as follows: ? full speed usb device controller compatible with the usb specification version 1.1 ? dma interface for bulk transfer ? 5 endpoints with fifo ep0: 16byte (register) ep1: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ep2: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ep3: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ep4: 128byte in/out fifo (dual port asynchronous ram): interrupt or dma ? integrated usb transceiver feature ? fully compliant with usb specification version 1.1 ? full speed (12mbps) device ? integrated usb transceiver ? supports control, interrupt and bulk transfer ? 5 endpoints with fifo: one bi-directional control endpoint with 16-byte fifo (ep0) four bi-directional bulk endpoint with 128-byte fifo (ep1, ep2, ep3, ep4) ? supports dma interface for receive and transmit bulk endpoints. (ep1, ep2, ep3, ep4) ? independent 128byte receive and transmit fifo to maximize throughput ? supports suspend and remote wake-up function
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-2 sie rt_vp_out rt_vm_in rt_vp_in rxd rt_uxsuspend rt_ux_oen rt_vm_out mc_addr[13:0] siu gfi fifos mcu & dma i/f mc_data_in[31:0] mc_data_out[31:0] usb_clk sys_clk sys_resetn mc_wr wr_rdn mc_csn mc_intr dreqn[3:0] dackn[3:0] figure 18-1. usb device block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-3 usb device special registers this section describes the detail functionality about register set usb device.. all special function register is byte access or word access. all reserved bit is zero. common indexed registers depend on index_reg(offset addre ss : 0x178) value. for example if you want to write ep0 csr register, you must write ?0x00? on index_reg before writing in csr1 register. all register must be resettled after host reset signaling. register name description offset address non indexed registers func_addr_reg function address register 0x140 pwr_reg power management register 0x144 ep_int_reg (ep0?ep4) endpoint interrupt register 0x148 usb_int_reg usb interrupt register 0x158 ep_int_en_reg (ep0?ep4) endpoint interrupt enable register 0x15c usb_int_en_reg usb interrupt enable register 0x16c frame_num1_reg frame number 1 register 0x170 frame_num2_reg frame number 2 register 0x174 index_reg index register 0x178 ep0_fifo_reg endpoint0 fifo register 0x1c0 ep1_fifo_reg endpoint1 fifo register 0x1c4 ep2_fifo_reg endpoint2 fifo register 0x1c8 ep3_fifo_reg endpoint3 fifo register 0x1cc ep4_fifo_reg endpoint4 fifo register 0x1d0 ep1_dma_con endpoint1 dma control register 0x200 ep1_dma_unit endpoint1 dma unit counter register 0x204 ep1_dma_fifo endpoint1 dma fifo counter register 0x208 ep1_dma_ttc_l endpoint1 dma transfer counter low-byte register 0x20c ep1_dma_ttc_m endpoint1 dma transfer counter middle-byte register 0x210 ep1_dma_ttc_h endpoint1 dma transfer counter high-byte register 0x214
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-4 ep2_dma_con endpoint2 dma control register 0x218 ep2_dma_unit endpoint2 dma unit counter register 0x21c ep2_dma_fifo endpoint2 dma fifo counter register 0x220 ep2_dma_ttc_l endpoint2 dma transfer counter low-byte register 0x224 ep2_dma_ttc_m endpoint2 dma transfer counter middle-byte register 0x228 ep2_dma_ttc_h endpoint2 dma transfer counter high-byte register 0x22c ep3_dma_con endpoint3 dma control register 0x240 ep3_dma_unit endpoint3 dma unit counter register 0x244 ep3_dma_fifo endpoint3 dma fifo counter register 0x248 ep3_dma_ttc_l endpoint3 dma transfer counter low-byte register 0x24c ep3_dma_ttc_m endpoint3 dma transfer counter middle-byte register 0x250 ep3_dma_ttc_h endpoint3 dma transfer counter high-byte register 0x254 ep4_dma_con endpoint4 dma control register 0x258 ep4_dma_unit endpoint4 dma unit counter register 0x25c ep4_dma_fifo endpoint4 dma fifo counter register 0x260 ep4_dma_ttc_l endpoint4 dma transfer counter low-byte register 0x264 ep4_dma_ttc_m endpoint4 dma transfer counter middle-byte register 0x268 ep4_dma_ttc_h endpoint4 dma transfer counter high-byte register 0x26c common indexed registers maxp_reg endpoint max packet register 0x180 in indexed registers in_csr1_reg ep in control status register 1 0x184 in_csr2_reg ep in control status register 2 0x188 out indexed registers out_csr1_reg ep out control status register 1 0x190 out_csr2_reg ep out control status register 2 0x194 out_fifo_cnt1_reg ep out write count register 1 0x198 out_fifo_cnt2_reg ep out write count register 2 0x19c
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-5 func_addr_reg this register maintains the usb device address a ssigned by the host. the mcu writes the value received through a set_address descriptor to this register. this address is used for the next token. register address r/w description reset value func_addr_reg 0x44a00140 r/w (byte) function address register 0x00 func_addr_re g bit mcu usb description initial state addr_update [7] r/w r /clear the mcu sets this bit whenever it updates the function_addr field in this register. this bit will be cleared by usb when data_end bit in ep0_csr register. 0 function_addr [6:0] r/w r the mcu write the unique address, assigned by host, to this field. 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-6 power management register (pwr_reg) this register is power control register in usb block. register address r/w description reset value pwr_reg 0x44a00144 r/w (byte) power management register 0x00 func_addr bit mcu usb description initial state reserved [31:9] reserved 0 iso_update [7] r/w r used for iso mode only. if set, gfi waits for a sof token to set in_pkt_rdy even though a packet to send is already loaded by mcu. if an in token is received before a sof token, then a zero length data packet will be sent. 0 reserved [6:4] - - reserved - usb_reset [3] r set the usb sets this bit if reset signaling is received from the host. this bit remains set as long as reset signaling persists on the bus 0 mcu_resume [2] r/w r /clear the mcu sets this bit for mcu resume. the usb generates the resume signaling depending resume con register, while this bit is set in suspend mode. suspend_mode [1] r set /clear this bit can be set by usb, automatically when the device enter into suspend mode. it is cleared under the following conditions 1) the mcu clears the mcu_resume bit by writing ?0?, to end remote resume signaling. 2) the resume signal form host is received. 0 suspend_en [0] r/w r suspend mode enable control bit 0 = disable(default). the device will not enter suspend mode. 1 = enable suspend mode 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-7 interrupt register (ep_int_reg, usb_int_reg) the usb core has two interrupt registers. these registers act as status registers for the mcu when it is interrupted. the bits are cleared by writing a ?1?(not ?0?) to each bit that was set. once the mcu is interrupted, mcu should read the contents of interrupt-related registers and write back to clear the contents if it is necessary. register address r/w description reset value ep_int_reg 0x44a00148 r/w (byte) ep interrupt pending/clear register 0x00 ep_int_reg bit mcu usb description initial state ep1~ep4 interrupt [4:1] r /clear set for bulk/interrupt in endpoints: the usb sets this bit under the following conditions: 1. in_pkt_rdy bit is cleared. 2. fifo is flushed 3. sent_stall set. for bulk/interrupt out endpoints: usb sets this bit under the following conditions: 1. sets out_pkt_rdy bit 2. sets sent_stall bit for iso in endpoints: the usb sets this bit under the following conditions: 1. under_run bit is set 2. in_pkt_rdy bit is cleared. 3. fifo is flushed note: conditions 1 and 2 are mutually exclusive for iso out endpoints: usb sets this bit under the following conditions: 1. out_pkt_rdy bit is set 2. over run bit is set. note: conditions 1 and 2 are mutually exclusive. 0 ep0 interrupt [0] r /clear set this bit corresponds to endpoint 0 interrupt the usb sets this bit under the following conditions: 1. out_pkt_rdy bit is set. 2. in_pkt_rdy bit is cleared. 3. sent_stall bit is set 4. setup_end bit is set 5. data_end bit is cleared(indicates end of control transfer) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-8 register address r/w description reset value usb_int_reg 0x44a00158 r/w (byte) usb interrupt pending/clear register 0x00 usb_int_reg bit mcu usb description initial state reset interrupt [2] r /clear set the usb set this bit, when it receives reset signaling. 0 resume interrupt [1] r /clear set the usb sets this bit, when it receives resume signaling, while in suspend mode . if the resume is due to a usb reset, then the mcu is first interrupted with a resume interrupt. once the clocks resume and the se0 condition persists for 3ms, usb reset interrupt will be asserted. 0 suspend interrupt [0] r /clear set the usb sets this bit when it receives suspend signalizing. this bit is set whenever there is no activity for 3ms on the bus. thus, if the mcu does not stop the clock after the first suspend interrupt, it will be continue to be interrupted every 3ms as long as there is no activity on the usb bus. by default this interrupt is disabled. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-9 interrupt enable register (ep_int_en_reg, usb_int_reg) corresponding to each interrupt register, there is an interrupt enable register (except resume interrupt enable). by default usb reset interrupt is enabled. if bit = 0, the interrupt is disabled if bit = 1, the interrupt is enabled register address r/w description reset value ep_int_en_reg 0x44a0015c r/w (byte) determines which interrupt is enabled. 0xff int_mask_reg bit mcu usb description initial state ep4_int_en [4] r/w r ep4 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep3_int_en [3] r/w r ep3 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep2_int_en [2] r/w r ep2 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep1_int_en [1] r/w r ep1 interrupt enable bit 0 = interrupt disable 1 = enable 1 ep0_int_en [0] r/w r ep0 interrupt enable bit 0 = interrupt disable 1 = enable 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-10 register address r/w description reset value usb_int_en_reg 0x44a0016c r/w (byte) determines which interrupt is enabled. 0x04 int_mask_reg bit mcu usb description initial state reset_int_en [2] r/w r reset interrupt enable bit 0 = interrupt disable 1 = enable 1 reserved [1] - - - 0 suspend_int_en [0] r/w r suspend interrupt enable bit 0 = interrupt disable 1 = enable 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-11 frame number register (fpame _num1_reg, frame_num2_reg) when host transfer usb packet, there is frame number in sof(start of frame). the usb catch this frame number and load it into this register, automatically. register address r/w description reset value frame_num1_reg 0x44a00170 r (byte) frame number lower byte register 0x00 frame_num_reg bit mcu usb description initial state frame_num1 [7:0] r w frame number lower byte value 00 register address r/w description reset value frame_num2_reg 0x44a00174 r (byte) frame number higher byte register 0x00 frame_num_reg bit mcu usb description initial state frame_num2 [7:0] r w frame number higher byte value 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-12 index register (index_reg) this index register is used to indicate certain endpoint registers effectively. mcu can access the endpoint registers(maxp_reg,in_csr1_reg,in_csr2_reg,out_csr1_reg,out_csr2_reg,out_fifo_cnt1_ reg,out_fifo_cnt2_reg) for an endpoint inside the core using the index register. register address r/w description reset value index_reg 0x44a00178 r/w (byte) register index register 0x00 index_reg bit mcu usb description initial state index [7:0] r/w r it indicates a certain endpoint. 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-13 end point0 control status register (ep0_csr) this register has the control and status bits for endpoint 0. since a control transaction involves both in and out tokens, there is only one csr register, mapped to the in csr1 register. (share in1_csr and can access by writing i ndex register ?0? and read/write in1_csr) register address r/w description reset value ep0_csr 0x44a00184 r/w (byte) endpoint 0 status register 0x00 ep0_csr bit mcu usb description initial state serviced_se tup_end [7] w clear the mcu should write a "1" to this bit to clear setup_end 0 serviced_ou t_pkt_rdy [6] w clear the mcu should write a "1" to this bit to clear out_pkt_rdy 0 send_stall [5] r/w clear mcu should writes a "1" to this bit at the same time it clears out_pkt_rdy, if it decodes an invalid token. 0 = finish the stall condition 1 = the usb issues a stall and shake to the current control transfer. 0 setup_end [4] r set the usb sets this bit when a control transfer ends before data_end is set. when the usb sets this bit, an interrupt is generated to the mcu. when such a condition occurs, the usb flushes the fifo and invalidates mcu access to the fifo. 0 data_end [3] set clear the mcu sets this bit below conditions: 1. after loading the last packet of data into the fifo, at the same time in_pkt_rdy is set. 2. while it clears out_pkt_rdy after unloading the last packet of data. 3. for a zero length data phase. 0 sent_stall [2] cle ar set the usb sets this bit if a control transaction is stopped due to a protocol violation. an interrupt is generated when this bit is set. the mcu should write "0" to clear this bit. 0 in_pkt_rdy [1] set clear the mcu sets this bit after writing a packet of data into ep0 fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when the usb clears this bit, so as the mcu to load the next packet. for a zero length data phase, the mcu sets data_end at the same time. 0 out_pkt_rdy [0] r set the usb sets this bit once a valid token is written to the fifo. an interrupt is generated when the usb sets this bit. the mcu clears this bit by writing a "1" to the serviced_out_pkt_rdy bit. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-14 end point in control status re gister (in_csr1_reg, in_csr2_reg) register address r/w description reset value in_csr1_reg 0x44a00184 r/w (byte) in end point control status register1 0x00 in_csr1_reg bit mcu usb description initial state reserved [7] - - - 0 clr_data_ toggle [6] r/w r/ clear this bit can be used in set-up procedure. 0 : there are alternation of data0 and data1 1 : the data toggle bit is cleared and pid in packet will maintain data0 0 sent_stall [5] r/ clear set the usb sets this bit when an in token issues a stall handshake, after the mcu sets send_stall bit to start stall handshaking. when the usb issues a stall handshake, in_pkt_rdy is cleared 0 send_stall [4] w/r r 0 : the mcu clears this bit to finish the stall condition. 1 : the mcu issues a stall handshake to the usb. 0 fifo_flush [3] w/ clear clear the mcu sets this bit if it intends to flush the packet in input-related fifo. this bit is cleared by the usb when the fifo is flushed. the mcu is interrupted when this happens. if a token is in process, the usb waits until the transmission is complete before fifo flushing. if two packets are loaded into the fifo, only first packet (the packet is intended to be sent to the host) is flushed, and the corresponding in_pkt_rdy bit is cleared 0 under_run [2] r/ clear set valid for iso mode only the usb sets this bit when in iso mode, an in token is received and the in_pkt_rdy bit is not set. the usb sends a zero length data packet for such conditions, and the next packet that is loaded into the fifo is flushed. this bit is cleared by writing 0. 0 reserved [1] - - - 0 in_pkt_rdy [0 r/set clear the mcu sets this bit, after writing a packet of data into the fifo. the usb clears this bit once the packet has been successfully sent to the host. an interrupt is generated when te usb clears this bit, so the mcu can load the next packet. while this bit is set, the mcu will not be able to write to the fifo. if the send stall bit is set by the mcu, this bit cannot be set. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-15 register address r/w description reset value in_csr2_reg 0x44a00188 r/w (byte) in end point control status register2 0x20 in_csr1_reg bit mcu usb description initial state auto_set [7] r/w r if set, whenever the mcu writes maxp data, in_pkt_rdy will automatically be set by the core, without any intervention from mcu. if the mcu writes less than maxp data, then in_pkt_rdy bit has to be set by the mcu. 0 iso [6] r/w r this bit is used only for endpoints whose transfer type is programmable. ?1? configures endpoint to iso mode ?0? configures endpoint to bulk mode 0 mode_in [5] r/w r this bit is used only for endpoints whose direction is programmable. ?1? configures endpoint direction as in ?0? configures endpoint direction as out 1 in_dma_int_en [4] r/w r this bit determi nes whether the interrupt should be issued, or not, when the ep1 in_pkt_rdy condition happens. this is only useful for dma mode. 0 = interrupt enable, 1 = interrupt disable 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-16 end point out control status regis ter(out_csr1_reg, out_csr2_reg) register address r/w description reset value out_csr1_reg 0x44a00190 r/w (byte) end point out control status register1 0x00 out_csr1_reg bit mcu usb description initial state clr_data_toggle [7] r/w clear when the mcu writes a 1 to this bit, the data toggle sequence bit is reset to data0. 0 sent_stall [6] clear /r set the usb sets this bit when an out token is ended with a stall handshake. the usb issues a stall handshake to the host if it sends more than maxp data for the out token. 0 send_stall [5] r/w r 0 : the mcu clears this bit to end the stall condition handshake, in pkt rdy is cleared. 1 : the mcu issues a stall handshake to the usb. the mcu clears this bit to end the stall condition handshake, in pkt rdy is cleared. 0 fifo_flush [4] r/w clear the mcu write a 1 to flush the fifo. this bit can be set only when out_pkt_rdy (d0) is set. the packet due to be unloaded by the mcu will be flushed. 0 data_error [3] r r/w this bit is valid only in iso mode. this bit should be sampled with out_pkt_rdy . when set, it indicates the data packet due to be unloaded by the mcu has an error (either bit stuffing or crc). if two packets are loaded into the fifo, and the second packet has an error, then this bit gets set only after the first packet is unloaded. this bit is automatically cleared when out_pkt_rdy gets cleared. 0 over_run [2] r/clear r/w this bit is valid only in iso mode. this bit is set if the core is not able to load an out iso token into the fifo. mcu clears this bit by writing 0. 0 reserved [1] - - - 0 out_pkt_rdy [0] r/ clear set the usb sets this bit after it has loaded a packet of data into the fifo. once the mcu reads the packet from fifo, this bit should be cleared by mcu. (write a "0") 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-17 register address r/w description reset value out_csr2_reg 0x44a00194 r/w (byte) end point out control status register2 0x00 out_csr2_reg bit mcu usb description initial state auto_clr [7] r/w r if mcu set, whenever the mcu reads data from the out fifo, out_pkt_rdy will automatically be cleared by the logic, without any intervention from mcu. 0 iso [6] r/w r this bit determines endpoint transfer type. ?0? : configures endpoint to bulk mode. ?1? : configures endpoint to iso mode 0 out_dma_int_en [5] r/w r this bit determines whether the interrupt should be issued, or not. out_pkt_rdy condition happens. this is only useful for dma mode 0 = interrupt enaebl 1 = interrupt disable 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-18 end point fifo register (epn_fifo_reg) to access epn fifo, the mcu should access epn_fifo_reg. register address r/w description reset value ep0_fifo 0x44a001c0 r/w (byte) end point0 fifo register 0xxx ep1_fifo 0x44a001c4 r/w (byte) end point1 fifo register 0xxx ep2_fifo 0x44a001c8 r/w (byte) end point2 fifo register 0xxx ep3_fifo 0x44a001cc r/w (byte) end point3 fifo register 0xxx ep4_fifo 0x44a001d0 r/w (byte) end point4 fifo register 0xxx epn_fifo bit mcu usb description initial state fifo_data [7:0] r/w r/w fifo data value 0xxx
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-19 max packet register (maxp_reg) register address r/w description reset value maxp_reg 0x44a00180 r/w (byte) end point max packet register 0x01 maxp_reg bit mcu usb description initial state maxp [3:0] r/w r 0000 : reserved 0001 : maxp = 8 byte 0010 : maxp = 16 byte 0100 : maxp = 32 byte 1000 : maxp = 64 byte 0001
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-20 end point out write count register(ou t_fifo_cnt1_reg, out_fifo_cnt2_reg) these registers maintain the number of bytes in the packet due to be unloaded by the mcu. register address r/w description reset value out_fifo_cnt1_reg 0x44a00198 r (byte) end point out write count register1 0x00 out_fifo_cnt1_reg bit mcu usb description initial state out_cnt_low [7:0] r w lower byte of write count 00 register address r/w description reset value out_fifo_cnt2_reg 0x44a0019c r (byte) end point out write count register2 0x00 out_fifo_cnt2_reg bit mcu usb description initial state out_cnt_high [7:0] r w higher byte of write count 00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-21 dma interface control register (epn_dma_con) register address r/w description reset value ep1_dma_con 0x44a00200 r/w (byte) ep1 dma interface control register 0x00 ep2_dma_con 0x44a00218 r/w (byte) ep2 dma interface control register 0x00 ep3_dma_con 0x44a00240 r/w (byte) ep3 dma interface control register 0x00 ep4_dma_con 0x44a00258 r/w (byte) ep4 dma interface control register 0x00 epn_dma_con bit mcu usb description initial state in_run_ob [7] r w in dma run observation 0 state [6:4] r w dma state monitoring 0 demand_mode [3] r/w r dma demand mode enable bit ?0? : demand mode disable ?1? : demand mode enable 0 out_run_ob / out_dma_run [2] r/w r/w this bit function is separated write and read operation write operation: ?0? = stop ?1? = run read operation: out dma run observation 0 in_dma_run [1] r/w r this bit is used to start dma operation 0 = stop 1 = run 0 dma_mode_en [0] r/w r this bit is used to set dma mode 0 = interrupt mode 1 = dma mode 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-22 dma unit counter register (epn_dma_unit) this register is valid in demand mode. in case not demand mode, this register value must be set ?0x01? register address r/w description reset value ep1_dma_unit 0x44a00204 r/w (byte) ep1 dma transfer unit counter base register 0x00 ep2_dma_unit 0x44a0021c r/w (byte) ep2 dma transfer unit counter base register 0x00 ep3_dma_unit 0x44a00244 r/w (byte) ep3 dma transfer unit counter base register 0x00 ep4_dma_unit 0x44a0025c r/w (byte) ep4 dma transfer unit counter base register 0x00 dma_unit bit mcu usb description initial state epn_unit_cnt [7:0] r/w r ep dma transfer unit counter value 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor usb device 18-23 dma fifo counter register (epn_dma_fifo) this register has byte size in fifo to be transferred by dma. in case out_dma_run enable, the value in out fifo write count register1 will be loaded in this register automatically. in case of in dma mode, the mcu should set proper value by s/w. register address r/w description reset value ep1_dma_fifo 0x44a00208 r/w (byte) ep1 dma transfer fifo counter base register 0x00 ep2_dma_fifo 0x44a00220 r/w (byte) ep2 dma transfer fifo counter base register 0x00 ep3_dma_fifo 0x44a00248 r/w (byte) ep3 dma transfer fifo counter base register 0x00 ep4_dma_fifo 0x44a00260 r/w (byte) ep4 dma transfer fifo counter base register 0x00 dma_fifo bit mcu usb descr iption initial state epn_fifo_cnt [7:0] r/w r ep dma transfer fifo counter value 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. usb device S3C24A0 risc microprocessor 18-24 dma total transfer counter register (epn_d ma_ttc_l, epn_dma_ttc_m, epn_dma_ttc_h) this register should have total number of bytes to be transferred using dma.(total 24bit counter) register address r/w description reset value ep1_dma_ttc_l 0x44a0020c r/w (byte) ep1 dma total transfer counter(lower byte) 0x00 ep1_dma_ttc_m 0x44a00210 r/w (byte) ep1 dma total transfer counter(middle byte) 0x00 ep1_dma_ttc_h 0x44a00214 r/w (byte) ep1 dma total transfer counter(higher byte) 0x00 ep2_dma_ttc_l 0x44a00224 r/w (byte) ep2 dma total transfer counter(lower byte) 0x00 ep2_dma_ttc_m 0x44a00228 r/w (byte) ep2 dma total transfer counter(middle byte) 0x00 ep2_dma_ttc_h 0x44a0022c r/w (byte) ep2 dma total transfer counter(higher byte) 0x00 ep3_dma_ttc_l 0x44a0024c r/w (byte) ep3 dma total transfer counter(lower byte) 0x00 ep3_dma_ttc_m 0x44a00250 r/w (byte) ep3 dma total transfer counter(middle byte) 0x00 ep3_dma_ttc_h 0x44a00254 r/w (byte) ep3 dma total transfer counter(higher byte) 0x00 ep4_dma_ttc_l 0x44a00264 r/w (byte) ep4 dma total transfer counter(lower byte) 0x00 ep4_dma_ttc_m 0x44a00268 r/w (byte) ep4 dma total transfer counter(middle byte) 0x00 ep4_dma_ttc_h 0x44a0026c r/w (byte) ep4 dma total transfer counter(higher byte) 0x00 dma_tx bit mcu usb description initial state epn_ttc_l [7:0] r/w r dma total transfer count value(lower byte) 0x00 epn_ttc_m [7:0] r/w r dma total transfer count value(middle byte) 0x00 epn_ttc_h [7:0] r/w r dma total transfer count value(higher byte) 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor modem interface 19-1 modem interface (preliminary) overview this specification defines the interface between the base-band modem and the application processor for the data-exchange of these two devices (refer figure 19-1). for the data-exchange, the ap (application processor, S3C24A0) has a dual-ported sram buffer (on-chip) and the modem chip can access that sram buffer using a typical asynchronous-sram interface. typically, the size of the sram buffer is 2kb. for the buffer status and interrupt requests, this specification also specifies a few of pre-defined special addresses. the modem chip can write data in the data buffer and write in terrupt control-data to the interrupt-port address for the interrupt request to the ap. the ap reads that dat a when an interrupt request is accepted and the interrupt is cleared when the ap accesses the interrupt-port address. in the same manner, the ap can write data in the data buffer and write interrupt control-data to the interrupt-port address for the interrupt request to the modem chip. modem chip application processor (S3C24A0) internal sram buffer address & control signals data interrupt request interrupt request to up embedded up figure 19-1 modem interface overview
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. modem interface S3C24A0 risc microprocessor 19-2 features ? 8-bit parallel bus for data transfer ? 2k bytes internal sram buffer ? interrupt request for data exchange ? programmable interrupt port address
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor modem interface 19-3 hardware interface the modem chip can access using an external memory interface (for example external sram). in this specification, the modem chip can access the internal sram and special address ports of the ap using the 8-bit data-bus and the 2k-byte address-space (i.e. 8-bit data-bus and 11-bit address bus). signal description name i/o 1) active description xmiirqn o l interrupt request to the modem chip xmidata [7:0] b - data bus, driven by the modem chip xmiadr[10:0] i - address bus, driven by the modem chip xmicsn i l chip select, driven by the modem chip xmiwen i l write enable, driven by the modem chip xmioen i l read enable, driven by the modem chip note 1) i/o direction is on the ap side. i : input o : output b : bi-direction table 19-1 modem interface signal description interrupt ports interrupts are requested or cleared if the modem chip or the ap accesses the interrupt-port (predefined special addresses). that special addresses can be configured by the ap and the default address-map is shown in the table19-2. address 1) an interrupt is requested, when the interrupt is cleared, when 0x7fe the modem chip writes see note 2 2) 0x7ff the ap writes the modem chip reads note 1) this address is default value. it can be set to the other value by the sfr. note 2) the interrupt is cleared by the interrupt controller of S3C24A0 table 19-2 interrupt ports and interrupt-request/clear conditions modem chip or ap(S3C24A0) can read the data that indicates what event happens ? data transfer requested, data transfer done, special command issued, etc. - from in terrupt port address. that data format should be defined for communication between the modem chip and ap.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. modem interface S3C24A0 risc microprocessor 19-4 address mapping 0x000 0x001 0x002 0x7ff 0x000 0x004 0x008 0x7fc 0x7fe 0x7fd 0x7fc 0x003 0x00c 0x41100000 0x41100004 0x41100008 0x411007fc 0x4110000c modem (byte) buffer (word) address map of 24a0 (word) 2k bytes buffer area 0x41180000 0x41180004 sfr modem interface area figure 19-2 modem interface address mapping
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor modem interface 19-5 timing diagram xmiadr xmicsn xmiwen xmidata t avwr t csvwr t dhwr t wr t dsuwr t awr figure 19-3 modem interface write timing diagram parameter description min (ns) max (ns) notes t avwr address valid to address invalid 11 ns - t csvwr chip select active 11 ns - t awr address valid to write active 2 ns - t wr write active 5 ns - t dsuwr write data setup 3 ns - t dhwr write data hold 4 ns - table 19-3 modem interface write timing
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. modem interface S3C24A0 risc microprocessor 19-6 xmiadr xmicsn xmioen xmidata t avrd t csvrd t acsdv t rd t rdh t rddv t adh figure 19-4 modem interface read timing diagram parameter description min max notes t avrd address valid to address invalid 20 ns - t adh address hold 2.5 ns - t csvrd chip select active 17.5 ns - t rd read active 17 ns - t rddv read active to data valid - 11.5 ns t rdh read data hold 4 ns - t acsdv address and chip select active to data valid - 12 ns note ) output load is 30pf at room temperature (25c) table 19-4 modem interface read timing
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor modem interface 19-7 software interface this modem interface provides a generic data-exchange method. this interface does not implement any other complex features except for the interrupt-request/clear such as automatic fifo managements, etc. the software should be responsible for all other required functionalities for the data exchange between the modem chip and the ap such as the data exchange protocol, the data buffer managements, and etc. modem interface special registers interrupt request to ap register (int2ap) register address r/w description reset value int2ap 0x41180000 r/w interrupt r equest to ap register 0x000007fe int2ap bit description initial state reserved [31:11] reserved 0 int2ap_adr [10:0] modem interface requests the interrupt to ap when modem chip writes this address. this interrupt is cleared by the interrupt controller of ap. 7fe interrupt request to modem register (int2mdm) register address r/w description reset value int2mdm 0x41180004 r/w interrupt request to modem register 0x000007ff int2mdm bit description initial state reserved [31:11] reserved 0 int2mdm_adr [10:0] modem interface requests the interrupt to modem chip when ap writes this address and clears the interrupt when modem chip reads this address. 7ff note ) it is recommended that ap writes data with byte access on the interrupt port because ap can overwrite the data in int2ap if there are int2ap and int2mdm sharing the same word.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. modem interface S3C24A0 risc microprocessor 19-8 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-1 general purpose i/o ports (preliminary) overview the S3C24A0 has 32 multi-functional general-purpose input/output port pins (gpio). each port can be easily configured by software to meet various system configuration and design requirements. you have to define which function of each pin is used before starting the main program. if the multiplexed functions on a pin are not used, the pin can be configured as i/o ports. the gpio module in the S3C24A0 has control-registers to configure the power-saving features for the whole chip interface. for example, it contains the control registers for the pin-status of the S3C24A0 that is in the sleep state (the sleep state is the state that the power source for the whole chip is off except for the power- management circuitry). for the normal mode operation, the gpio pins can be fully configured as an input port with or without pull-up register, an output port, a specific functional pin or an external interrupt source.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-2 table 20-1. S3C24A0 port configuration overview port selectable pin functions (refers the gpio port configuration registers ? gpcon_u, gpcon_m & gpcon_l.) gp31 input/output xurxd1 irda_rxd gp30 input/output xutxd1 irda_txd gp29 input/output xurtsn1 irda_sdbw gp28 input/output xuctsn1 rtc_almint gp27 input/output extdma_ack1 xkpcol4 gp26 input/output extdma_ack0 xkpcol3 gp25 input/output extdma_req1 xkpcol2 gp24 input/output extdma_req0 xkpcol1 gp23 input/output pwm_tout3 xkpcol0 gp22 input/output pwm_tout2 xkprow4 gp21 input/output pwm_tout1 xkprow3 gp20 input/output pwm_tout0 xkprow2 gp19 input/output pwm_eclk xkprow1 gp18 input/output eint18 xkprow0 gp17 input/output eint17 xspiclk gp16 input/output eint16 xspimiso gp15 input/output eint15 xspimosi gp14 input/output eint14 rtc_almint gp13 input/output eint13 reserved gp12 input/output eint12 reserved gp11 input/output eint11 reserved gp10 input/output reserved reserved gp9 input/output eint9 extdma_ack1 gp8 input/output eint8 extdma_ack0 gp7 input/output eint7 extdma_req1 gp6 input/output eint6 extdma_req0 gp5 input/output eint5 pwm_tout3 gp4 input/output eint4 pwm_tout2 gp3 input/output eint3 pwm_tout1 gp2 input/output eint2 pwm_tout0 gp1 input/output eint1 pwm_eclk gp0 input/output eint0 -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-3 port control descriptions gpio port configuration register for norm al mode (gpcon_u, gpcon_m, gpcon_l) in the S3C24A0, 32 pins are multiplexed pins. so, it is determined which function is selected for each pins. the pcon (port control register) determines which function is used for each pin. if gp0 ? gp9 are used for the wakeup signal in power down mode, these ports must be configured as an interrupt mode. the wake-up events are generated when the individual gpio pin is configured as an external interrupt mode regardless of the interrupt mask bits. gpio port data register for normal mode (gpdat) if ports are configured as output ports, data can be written to the corresponding bit of gpdat. if ports are configured as input ports, the data can be read from the corresponding bit of gpdat. gpio port pull-pu control register for normal mode (gppu) the port pull-up register controls the pull-up resister enable/disable of each port group. when the corresponding bit is 0, the pull-up resister of the pin is enabled. when 1, the pull-up resister is disabled. if the port pull-up register is enabled then the pull-up resisters work without pin?s functional setting (input, output, eintn and etc) external interrupt control register (ext intcn/ eintfltn/ eintmask/ eintpend) the 18 eint ports are requested by various signaling me thods. the extintc register configures the signaling method among the low level trigger, high level trigger, falling edge trigger, rising edge trigger, and both edge trigger for the external interrupt request all 18 eint ports generate an interrupt when each port is configured as the interrupt mode and the corresponding interrupt is unmasked. however, even if the interrupt is masked to a corresponding interrupt port (eintmask), an interrupt pending bit (eintpend) is set when the port is configured as the interrupt mode. the 8 eint ports have a digital filter. (refer to eintfltn register) only 10 eint ports (eint [9:0]) are used for wake-up sources. in the sleep mode, all wake-up sources are disabled when the nbatflt signal is asserted to low (it will not generate a wake-up event nor a interrupt is pending). wake-up source is updated in eintpend including rtc alarm wake-up bit. peripheral port pull-up control re gister for normal mode (peripu) the peripheral port pull-up control register controls internal pull-up resister attached to the corresponding port pin. when the corresponding bit is 0, the pull-up resister of the pin is enabled. when 1, the pull-up resister is disabled. alive control register (alivecon) these bits notify what kind of reset occurred and battery fault has occurred or not.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-4 gpio output data register for sleep mode (gpdat_sleep) gpio port output data register in sleep mode. in sleep mode the value of gpdat is meaningless. gpio output control register for sleep mode (gpoen_sleep) gpio port output control register for each port in sleep mode. in sleep mode the value of gpcon is meaningless. gpio pull-up control register for sleep mode (gppu_sleep) control pull up resister attached to the corresponding gpio port pin in sleep mode. in sleep mode the value of gppu is meaningless. peripheral port output data registe r for sleep mode (peridat_sleepn) peripheral port output data register in sleep mode. peripheral port output control regis ter for sleep mode (perioen_sleepn) peripheral port output control register for each port in sleep mode. peripheral port pull-up control re gister for sleep mode (peripu_sleep) control pull up resister attached to the peripheral port in sleep mode. in sleep mode the value of peripu is meaningless. reset count compare register (rstcnt) these value control the duration of reset when wake-up from sleep mode. general purpose ram array (gpramn) general purpose ram array, 16 x 32 bit.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-5 i/o port control register gpio upper port control register (gpcon_u) register address r/w description reset value gpcon_u 0x44800000 r/w configures the pins of upper ports[31:19] 0x0 gpcon_u bit description gp31 [25:24] 00 = input 01 = output 10 = xurxd1 11 = irda_rxd gp30 [23:22] 00 = input 01 = output 10 = xutxd1 11 = irda_txd gp29 [21:20] 00 = input 01 = output 10 = xurtsn1 11 = irda_sdbw gp28 [19:18] 00 = input 01 = output 10 = xuctsn1 11 = rtc_almint gp27 [17:16] 00 = input 01 = output 10 = extdma_ack1 11 = xkpcol4 gp26 [15:14] 00 = input 01 = output 10 = extdma_ack0 11 = xkpcol3 gp25 [13:12] 00 = input 01 = output 10 = extdma_req1 11 = xkpcol2 gp24 [11:10] 00 = input 01 = output 10 = extdma_req0 11 = xkpcol1 gp23 [9:8] 00 = input 01 = output 10 = pwm_tout3 11 = xkpcol0 gp22 [7:6] 00 = input 01 = output 10 = pwm_tout2 11 = xkprow4 gp21 [5:4] 00 = input 01 = output 10 = pwm_tout1 11 = xkprow3 gp20 [3:2] 00 = input 01 = output 10 = pwm_tout0 11 = xkprow2 gp19 [1:0] 00 = input 01 = output 10 = pwm_eclk 11 = xkprow1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-6 gpio middle port control register (gpcon_m) if gp11 ? gp18 will be used for wakeup signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value gpcon_m 0x44800004 r/w configures the pins of middle ports[18:11] 0x0 gpcon_m bit description gp18 [15:14] 00 = input 01 = output 10 = eint18 11 = xkprow0 gp17 [13:12] 00 = input 01 = output 10 = eint17 11 = xspiclk gp16 [11:10] 00 = input 01 = output 10 = eint16 11 = xspimiso gp15 [9:8] 00 = input 01 = output 10 = eint15 11 = xspimosi gp14 [7:6] 00 = input 01 = output 10 = eint14 11 = rtc_almint gp13 [5:4] 00 = input 01 = output 10 = eint13 11 = reserved gp12 [3:2] 00 = input 01 = output 10 = eint12 11 = reserved gp11 [1:0] 00 = input 01 = output 10 = eint11 11 = reserved
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-7 gpio lower port control register (gpcon_l) if gp8 ? gp10 will be used for wakeup signals at power down mode, the ports will be set in interrupt mode. register address r/w description reset value gpcon_l 0x44800008 r/w configures the pins of lower ports[10:0] 0x0 gpcon_l bit description gp10 [21:20] 00 = input 01 = output 10 = reserved 11 = reserved gp9 [19:18] 00 = input 01 = output 10 = eint9 11 = extdma_ack1 gp8 [17:16] 00 = input 01 = output 10 = eint8 11 = extdma_ack0 gp7 [15:14] 00 = input 01 = output 10 = eint7 11 = extdma_req1 gp6 [13:12] 00 = input 01 = output 10 = eint6 11 = extdma_req0 gp5 [11:10] 00 = input 01 = output 10 = eint5 11 = pwm_tout3 gp4 [9:8] 00 = input 01 = output 10 = eint4 11 = pwm_tout2 gp3 [7:6] 00 = input 01 = output 10 = eint3 11 = pwm_tout1 gp2 [5:4] 00 = input 01 = output 10 = eint2 11 = pwm_tout0 gp1 [3:2] 00 = input 01 = output 10 = eint1 11 = pwm_eclk gp0 [1:0] 00 = input 01 = output 10 = eint0 11 = reserved
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-8 gpio port data register (gpdat) register address r/w description reset value gpdat 0x4480000c r/w the data register for all ports[31:0] undefined gpdat bit description gp[31:0] [31:0] when the port is configured as input port, data from external sources can be read to the corresponding pin. when the port is configured as output port, data written in this register can be sent to the corresponding pin. when the port is configured as function pin, undefined value will be read. gpio port pull up resister control register (gppu) register address r/w description reset value gppu 0x44800010 r/w pull-up disable register for all ports[31:0] 0x0 reserved 0x44800014 - reserved undefined gppu bit description gp[31:0] [31:0] 0 : the pull up function attached to to the corresponding port pin is enabled. 1 : the pull up function is disabled.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-9 external interrupt control register (extintc0) the 18 external interrupts can be requested by various signaling methods. the extintc register configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity. to recognize the level interrupt, the valid logic level on extintcn pin must be retained for 40ns at least because of the noise filter. (eint[9:0]) register address r/w description reset value extintc0 0x44800018 r/w external interrupt control register 0 0x0 extintc0 bit description reserved [11] this bit is reserved and the value should be ?0? extint2 [10:8] setting the signaling method of the eint2. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [7] this bit is reserved and the value should be ?0? extint1 [6:4] setting the signaling method of the eint1. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [3] this bit is reserved and the value should be ?0? extint0 [2:0] setting the signaling method of the eint0. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-10 external interrupt control register (extintc1) register address r/w description reset value extintc1 0x4480001c r/w external interrupt control register 1 0x0 extintc1 bit description reserved [31:27] this bit is reserved and the value should be ?0? extint9 [26:24] setting the signaling method of the eint9. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [23] this bit is reserved and the value should be ?0? extint8 [22:20] setting the signaling method of the eint8. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [19] this bit is reserved and the value should be ?0? extint7 [18:16] setting the signaling method of the eint7. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [15] this bit is reserved and the value should be ?0? extint6 [14:12] setting the signaling method of the eint6. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [11] this bit is reserved and the value should be ?0? extint5 [10:8] setting the signaling method of the eint5. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [7] this bit is reserved and the value should be ?0? extint4 [6:4] setting the signaling method of the eint4. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered reserved [3] this bit is reserved and the value should be ?0? extint3 [2:0] setting the signaling method of the eint3. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-11 external interrupt control register (extintc2) register address r/w description reset value extintc2 0x44800020 r/w external interrupt control register 2 0x0 extintc2 bit description flten18 [31] filter enable for eint18 0 = disable 1= enable extint18 [30:28] setting the signaling method of the eint18. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten17 [27] filter enable for eint17 0 = disable 1= enable extint17 [26:24] setting the signaling method of the eint17. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten16 [23] filter enable for eint16 0 = disable 1= enable extint16 [22:20] setting the signaling method of the eint16. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten15 [19] filter enable for eint15 0 = disable 1= enable extint15 [18:16] setting the signaling method of the eint15. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten14 [15] filter enable for eint14 0 = disable 1= enable extint14 [14:12] setting the signaling method of the eint14. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten13 [11] filter enable for eint13 0 = disable 1= enable extint13 [10:8] setting the signaling method of the eint13. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten12 [7] filter enable for eint12 0 = disable 1= enable extint12 [6:4] setting the signaling method of the extint12. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered flten11 [3] filter enable for eint11 0 = disable 1= enable extint11 [2:0] setting the signaling method of the eint11. 000 = low level 001 = high level 01x = falling edge triggered 10x = rising edge triggered 11x = both edge triggered
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-12 external interrupt filter control register (eintfltn) eintfltn control the length of filter for 8 external interrupts (eint[18:11]). register address r/w description reset value eintflt0 0x44800024 r/w external interrupt control register 0x0 eintflt1 0x44800028 r/w external interrupt control register 0x0 eintflt0 bit description fltclk14 [31] filter clock of eint14 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt14 [30:24] filtering width of eint14 fltclk13 [23] filter clock of eint13 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt13 [22:16] filtering width of eint13 fltclk12 [15] filter clock of eint12 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt12 [14:8] filtering width of eint12 fltclk11 [7] filter clock of eint11 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt11 [6:0] filtering width of eint11 eintflt1 bit description fltclk18 [31] filter clock of eint18 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt18 [30:24] filtering width of eint18 fltclk17 [23] filter clock of eint17 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt17 [22:16] filtering width of eint17 fltclk16 [15] filter clock of eint16 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt16 [14:8] filtering width of eint16 fltclk15 [7] filter clock of eint15 0 = pclk 1= xsextclk/xsxtin/rtc_clk note eintflt15 [6:0] filtering width of eint15 note: when the filter clock bit is ?1?, the source clock for filter is determined by the value of xgrefclksel[0] pin and the value of alivecon[0].
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-13 external interrupt mask register (eintmask)) interrupt mask register for 18 external interrupts (eint[18:11, 9:0]). register address r/w description reset value eintmask 0x44800034 r/w external interupt mask register 0x0007ffff eintmask bit description eint18 [18] 0 = enable interrupt 1= masked eint17 [17] 0 = enable interrupt 1= masked eint16 [16] 0 = enable interrupt 1= masked eint15 [15] 0 = enable interrupt 1= masked eint14 [14] 0 = enable interrupt 1= masked eint13 [13] 0 = enable interrupt 1= masked eint12 [12] 0 = enable interrupt 1= masked eint11 [11] 0 = enable interrupt 1= masked reserved [10] reserved eint9 [9] 0 = enable interrupt 1= masked eint8 [8] 0 = enable interrupt 1= masked eint7 [7] 0 = enable interrupt 1= masked eint6 [6] 0 = enable interrupt 1= masked eint5 [5] 0 = enable interrupt 1= masked eint4 [4] 0 = enable interrupt 1= masked eint3 [3] 0 = enable interrupt 1= masked eint2 [2] 0 = enable interrupt 1= masked eint1 [1] 0 = enable interrupt 1= masked eint0 [0] 0 = enable interrupt 1= masked
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-14 external interrupt pending register (eintpend) interrupt pending register for 18 external interrupts (eint[18:11, 9:0]). if the S3C24A0 wake-up from sleep mode by rtc alarm, the pmwkup bit is set instead of int_rtc bit in intpnd and intsrcpnd register. you can clear a specific bit of eintpend register by writing a data (?1?) to this register. it clears only the bit positions of eintpend corresponding to those set to one in the data. the bit positions corresponding to those that are set to 0 in the data remains as they are with no change. register address r/w description reset value eintpend 0x44800038 r/w external interupt pending register 0x0 eintpend bit description pmwkup [19] rtc alarm interrupt. 0 = not occur 1= occur interrupt eint18 [18] 0 = not occur 1= occur interrupt eint17 [17] 0 = not occur 1= occur interrupt eint16 [16] 0 = not occur 1= occur interrupt eint15 [15] 0 = not occur 1= occur interrupt eint14 [14] 0 = not occur 1= occur interrupt eint13 [13] 0 = not occur 1= occur interrupt eint12 [12] 0 = not occur 1= occur interrupt eint11 [11] 0 = not occur 1= occur interrupt reserved [10] reserved eint9 [9] 0 = not occur 1= occur interrupt eint8 [8] 0 = not occur 1= occur interrupt eint7 [7] 0 = not occur 1= occur interrupt eint6 [6] 0 = not occur 1= occur interrupt eint5 [5] 0 = not occur 1= occur interrupt eint4 [4] 0 = not occur 1= occur interrupt eint3 [3] 0 = not occur 1= occur interrupt eint2 [2] 0 = not occur 1= occur interrupt eint1 [1] 0 = not occur 1= occur interrupt eint0 [0] 0 = not occur 1= occur interrupt
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-15 peripheral port pull up control register (peripu) pull up control register for peripheral port in normal mode. register address r/w description reset value peripu 0x44800040 r/w controlled pull-up register 0x00004000 peripu bit description reserved [31:27] reserved peripu26 [26] pull-up for xmssdio port 0 : enabled 1 : disabled reserved [25] reserved peripu24 [24] pull-up for xsddat[3:0] ports 0 : enabled 1 : disabled reserved [23:15] reserved peripu14 [14] pull-up for xraddr[25:18] ports 0 : enabled 1 : disabled peripu13 [13] pull-up for xcicdata[7:0] ports 0 : enabled 1 : disabled peripu12 [12] pull-up for xmiadr[10:0] ports 0 : enabled 1 : disabled peripu11 [11] pull-up for xmidata[7:0] ports 0 : enabled 1 : disabled peripu10 [10] pull-up for xspiclk and xspimosi ports 0 : enabled 1 : disabled peripu9 [9] pull-up for x2slrck and x2sclk ports 0 : enabled 1 : disabled peripu8 [8] pull-up for xspimiso port 0 : enabled 1 : disabled reserved [7:5] reserved peripu4 [4] pull-up for xrdata[15:0] ports 0 : enabled 1 : disabled peripu3 [3] reserved peripu2 [2] pull-up for xpdata[31:0] ports 0 : enabled 1 : disabled reserved [1:0] reserved
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-16 alive control register (alivecon) alivecon register reports reset status and battery fault status. the clock for alive-block in sleep mode can be selected. register address r/w description reset value alivecon 0x44800044 r/w alive control register 0x0 alivecon bit description batflt [7] 0 ? battery fault has not been asserted 1 ? battery fault has been asserted softrst [6] 0 ? sw reset has not been asserted 1 ? sw reset has been asserted wdtrst [5] 0 ? watch-dog-timer reset has not been asserted 1 ? watch-dog-timer reset has been asserted warmrst [4] 0 ? warm reset has not been asserted 1 ? warm reset has been asserted reserved [3:2] reserved sleeprst [1] this bit does not set automatically. users must set this bit before enter sleep mode. 0 ? sleep mode wake-up operation has not been asserted 1 ? sleep mode wake-up operation has been asserted aliveclksel [0] xsxtin and xsextclk is selected by xgrefclksel[0] pin when the xgrefclksel[0] is high, the ext_clk is selected. 0 : xsxtin / xsextclk 1 : rtc_clk note: the asserted value, which is set automatically by hardware, should be cleared by software after checking the status.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-17 gpio output data register (gpdat_sleep) gpio port output data register in sleep mode. in sleep mode the value of gpdat is meaningless. register address r/w description reset value gpdat_sleep 0x44800048 r/w output data for sleep mode 0x0 gpdat_sleep bit description gpdat_sleep[31:0] [31:0] these value are propagated to corresponding ports/pins, if gpoen_sleep is activated at sleep mode. gpio output control register for sleep mode (gpoen_sleep) gpoen_sleep register controls gpio port with output or hi-z state. register address r/w description reset value gpoen_sleep 0x4480004c r/w gpio output enable control for sleep mode 0xffff_ffff gpoen_sleep bit description gpoen_sleep[31:0] [31:0] 0 : make gpio output port in sleep mode. 1 : make gpio hi-z state in sleep mode. gpio pull up control register for sleep mode (gppu_sleep) pull up control register for gpio port in sleep mode. register address r/w description reset value gppu_sleep 0x44800050 r/w gpio pull-up control register for sleep mode 0xffff_ffff gppu_sleep bit description gppu_sleep[31:0] [31:0] 0 : the pull up function attached to to the corresponding port pin is enabled in sleep mode. 1 : the pull up function is disabled in sleep mode.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-18 peripheral port output data registe r for sleep mode (peridat_sleep0) peripheral port output data register in sleep mode. these data is meaningful only when the perioen_sleep is enabled. register address r/w description reset value peridat_sleep0 0x44800054 r/w output data register for sleep mode 0x8095_a220 peridat_sleep0 bit description reset value peridat031 [31] xsrstoutn port output data 1 peridat030 [30] xmssdio and xsddat[3:0] ports output data 0 peridat029 [29] xmssclko and xmsbs ports output data 0 reserved [28] reserved 0 peridat027 [27] xvvd[17:0] ports output data 0 peridat026 [26] xvvsync, xvhsync and xvvclk ports output data 0 peridat025 [25 xcirstn port output data 0 peridat024 [24] xciclk port output data 0 peridat023 [23] xmiirqn port output data 1 peridat022 [22] xmidata[7:0] and xgmonhclk ports output data 0 peridat021 [21] xuddn port output data 0 peridat020 [20] xuddp port output data 1 peridat019 [19] xusdn[1:0] ports output data 0 peridat018 [18] xusdp[1:0] ports output data 1 peridat017 [17] x97sync and x97sdo ports output data 0 peridat016 [16] x97resetn port output data 1 peridat015 [15] xspiclk and xspimosi ports output data 1 peridat014 [14] x2scdclk and x2sdo ports output data 0 peridat013 [13] x2slrck and x2sclk ports output data 1 peridat012 [12] xutxd0 and xurts0 ports output data 0 reserved [11:8] reserved 2 peridat07 [7] xpdata[31:0] ports output data 0 peridat06 [6] xpdqm[3:0] and xpaddr[14:0] ports output data 0 peridat05 [5] xpcsn[1:0], xpcasn and xprasn ports output data 1 peridat04 [4] xpcke and xpsclk ports output data 0 peridat03 [3] xrdata[15:0] ports output data 0 peridat02 [2] xraddr[25:18] ports output data 0 peridat01 [1] xrcsn[2:0], xrwen, xroen and xrnwbe[1:0] ports output data 0 peridat00 [0] xfcle and xfale ports output data 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-19 peripheral port output data registe r for sleep mode (peridat_sleep1) peripheral port output data register in sleep mode. these data is meaningful only when the perioen_sleep is enabled. register address r/w description reset value peridat_sleep1 0x44800058 r/w output data register for sleep mode 0x8095_a220 peridat_sleep1 bit description reset value reserved [31:7] reserved 0 peridat16 [6] xpwen port output data 1 peridat15 [5] xjrtck port output data 1 peridat14 [4] x2cscl, x2csda ports output data 1 reserved [3] reserved 1 peridat12 [2] xraddr[17:0] ports output data 0 peridat11 [1] xspimiso port output data 1 peridat10 [0] xjtdo port output data 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-20 peripheral port output control re gister for sleep mode (perioen_sleep0) peripheral port output control register for each port in sleep mode. perioen_sleep[8, 6] bits are used for suspend enabler also in stop mode. register address r/w description reset value perioen_sleep0 0x4480005c r/w output control register0 for sleep mode 0x003f_03e3 perioen_sleep0 bit description reset value reserved [31:22] reserved 0 perioen021 [21] select xmidata[7:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 reserved [20:16] reserved 0x1f perioen015 [15] select xjtdo pin output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen014 [14] select xsxtout pin output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen013 [13] select xsddat[3:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen012 [12] select xmssdio pin output or hi-z 0: enable(output) 1: disable(hi-z) 0 reserved [11] reserved 0 perioen010 [10] select xvvd[17:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 reserved [9] reserved 1 perioen08 [8] select xuddp and xuddn pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 reserved [7] reserved 1 perioen06 [6] select xusdp[1:0] and xusdn[1:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen05 [5] select xspiclk and xspimosi pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen04 [4] select x2slrck and x2sclk pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen03 [3] select xspimiso pin output or hi-z 0: enable(output) 1: disable(hi-z) 0 reserved [2] reserved 0 perioen01 [1] select xpdata[31:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen00 [0] select xrdata[15:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-21 peripheral port output control re gister for sleep mode (perioen_sleep1) register address r/w description reset value perioen_sleep1 0x44800060 r/w output control register1 for sleep mode 0x0037_d802 perioen_sleep1 bit description reset value reserved [31:20] reserved 0x3 perioen119 [19] select xsrstoutn pin output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen118 [18] select xmsbs and xmssclko pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen117 [17] select xvden pin output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen116 [16] select xvvsync, xvhsync and xvvclk pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen115 [15] select xcirstn pin output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen114 [14] select xciclk pin output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen113 [13] select xmiirqn and xgmonhclk pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen112 [12] select x97sync and x97sdo pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen111 [11] select x97resetn pin output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen110 [10] select x2scdclk and x2sdo pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen19 [9] select xutxd0 and xurtsn0 pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 reserved [8:6] reserved 0 perioen15 [5] select xpdqm[3:0] and xpaddr[14:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen14 [4] select xpwen, xpcsn[1:0], xpcasn and xprasn pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen13 [3] select xpcke and xpsclk pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen12 [2] select xraddr[17:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 0 perioen11 [1] select xrcsn[2:0], xrwen, xroen and xrnwbe[1:0] pins output or hi-z 0: enable(output) 1: disable(hi-z) 1 perioen10 [0] select xfcle and xfale pins output or hi-z 0: enable(output) 1: disable(hi-z) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-22 peripheral port pull up control re gister for sleep mode (peripu_sleep) control pull up resister attached to the corresponding peripheral port pin in sleep mode. register address r/w description reset value peripu_sleep 0x44800064 r/w controlled pull-up register for slee mode 0x0 peripu_sleep bit description reserved [32:27] reserved peripu26 [26] control internal pull-up resister for xmssdio in sleep mode 0 : enabled 1 : disabled reserved [25] reserved peripu24 [24] control internal pull-up resister for xsddat[3:0] in sleep mode 0 : enabled 1 : disabled reserved [23:12] reserved peripu11 [11] control internal pull-up resister for xmidata[7:0] in sleep mode 0 : enabled 1 : disabled peripu10 [10] control internal pull-up resister for xspiclk and xspimosi in sleep mode 0 : enabled 1 : disabled peripu9 [9] control internal pull-up resister for x2slrck and x2sclk in sleep mode 0 : enabled 1 : disabled peripu8 [8] control internal pull-up resister for xspimiso in sleep mode 0 : enabled 1 : disabled reserved [7:5] reserved in sleep mode peripu4 [4] control internal pull-up resister for xrdata[15:0] in sleep mode 0 : enabled 1 : disabled reserved [3] reserved peripu2 [2] control internal pull-up resister for xpdata[31:0] in sleep mode 0 : enabled 1 : disabled reserved [1:0] reserved
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-23 reset count compare register (rstcnt) compared counter value for the power settle-down-time wait. register address r/w description reset value rstcnt 0x44800068 r/w reset count compare register 0x0 rstcnt bit description rstcnt[7:0] [7:0] after wake-up from the sleep mode, the S3C24A0 power-management logic adds an external power-source settle-down-wait time by holding the internal reset signal to low (forces the internal reset is active). the aliveclk is the reference clock source for the power-management circuitry. it can be selected from the external clock sources or the rtc clock. reset duration = (rstcnt[7] x 16384 rstcnt[6] x 3 x 2048 rstcnt[5] x 7 x 256 rstcnt[4] x 7 x 32 rstcnt[3] x 3 x 8 rstcnt[2:0] ) x 32 x 1/aliveclk
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. i/o ports S3C24A0 risc microprocessor 20-24 general purpose ram array (gpramn) general purpose ram array, 16x32-bit. these memory array connected alive-block, so their contents be maintained in sleep mode. register address r/w description reset value gpram0 0x44800080 r/w general purpose ram word 0 undefined gpram1 0x44800084 r/w general purpose ram word 1 undefined gpram2 0x44800088 r/w general purpose ram word 2 undefined gpram3 0x4480008c r/w general purpose ram word 3 undefined gpram4 0x44800090 r/w general purpose ram word 4 undefined gpram5 0x44800094 r/w general purpose ram word 5 undefined gpram6 0x44800098 r/w general purpose ram word 6 undefined gpram7 0x4480009c r/w general purpose ram word 7 undefined gpram8 0x448000a0 r/w general purpose ram word 8 undefined gpram9 0x448000a4 r/w general purpose ram word 9 undefined gpram10 0x448000a8 r/w general purpose ram word 10 undefined gpram11 0x448000ac r/w general purpose ram word 11 undefined gpram12 0x448000b0 r/w general purpose ram word 12 undefined gpram13 0x448000b4 r/w general purpose ram word 13 undefined gpram14 0x448000b8 r/w general purpose ram word 14 undefined gpram15 0x448000bc r/w general purpose ram word 15 undefined
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor i/o ports 20-25 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-1 camera interface (preliminary) overview this specification defines the interface of camera. t he camera interface of S3C24A0 consists of seven parts. they are the pattern mux, capturing unit, preview scale r, codec scaler, preview dm a, codec dma, and sfr. the camera interface supports itu r bt-601/656 ycbcr 8/16- bit standard. maximum input size is 4096x4096 pixels (2048x2048 pixels for scaling). there are two scalers. t he one is the preview scaler, which is dedicated to generate small size image as pip(picture in picture). t he other one is the codec sca ler, which is dedicated to generate codec useful image like plane type ycbcr 4:2:0 or 4:2:2. tw o master dmas can do mirroring and rotating the captured image for mobile environments. these f eatures are very useful at folder type cellular phone. and test pattern generation can be used to calibration of input sync signals as href,vsync. also, video sync signals and pixel clock polarity can be inverted in the camera interface side with using register setting. ycbcr 4:2:2 t_patternmux catchcam ycbcr 4:2:x preview scaler & rgb formatter codec scaler preview dma itu-r bt 601/656 codec dma camif sfr ahb bus figure 21-1. camera interface overview
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-2 features - itu-r bt 601/656 8/16-bit mode - dzi (digital zoom in) capability - programmable polarity of video sync signals - up to 4096 x 4096 pixel input (up to 2048 x 2048 pixel input for scaling) - image mirror and rotation (x-axis mirror, y-axis mirror, and 180rotation) - pip and codec input image generation (rgb 16/24- bit format and ycbcr 4:2:0/4:2:2 format) external interface the camera interface of S3C24A0 can support the next video standards. - itu-r bt 601 ycbcr 8/16-bit mode - itu-r bt 656 ycbcr 8-bit mode signal description name i/o 1) active description xcipclk i - pixel clock, driven by the camera processor xcivsync i h/l frame sync, driven by the camera processor xcihref i h/l horizontal sync, driven by the camera processor xciydata [7:0] i - pixel data for ycbcr in 8-bit mode or for y in 16-bit mode, driven by the camera processor xcicdata [7:0] i - pixel data for cbcr in 16-bit mode, driven by the camera processor xciclk o - master clock to the camera processor xcirstn o h/l software reset or power down for the camera processor note 1) i/o direction is on the S3C24A0 side. i : input, o : output, b : bi-direction table 21-1. camera interface signal description
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-3 timing diagram xcivsync y cb y cr y cb y cb y cr xcihref xcihref xcipclk xciydata[7:0] vertical lines horizontal width 1 frame xciydata[7:0] xcicdata[7:0] 8-bit mode 16-bit mode y y y y y y y y y y cb cr cb cr cb cr cb cr cb cr figure 21-2. itu-r bt 601 input timing diagram figure 21-3. itu-r bt 656 input timing diagram there are two timing reference signals in itu-r bt 656 format, one is at the beginning of each video data block (start of active video, sav) and the other is at the end of each video data block(end of active video, eav) as shown in figure 21-3 and table 21-2. data bit number first word second word third word fourth word 9 (msb) 1 0 0 1 8 1 0 0 f 7 1 0 0 v xcipclk xciydata[7:0] cr ff 00 00 xy cb y ff 00 00 xy video timing reference codes pixel data video timing reference codes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-4 6 1 0 0 h 5 1 0 0 p3 4 1 0 0 p2 3 1 0 0 p1 2 1 0 0 p0 1 (note 1) 1 0 0 0 01000 note 1) for compatibility with existing 8-bit interf aces, the values of bits d1 and d0 are not defined. f = 0 (during field 1), 1 (during field 2) v = 0 (elsewhere), 1 (during field blanking) h = 0 (in sav : start of active video), 1 (in eav : end of active video) p0, p1, p2, p3 = protection bit table 21-2. video timing reference codes of itu-656 format camera interface logic can catch the video sync bi ts like h(sav,eav) and v(frame sync) after reserved data as ?ff-00-00?.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-5 external connection guide all input signals of camera interface should not occu r inter-skewing to pixel clock line. recommend next pin location and routing. xcirstn xciclk xcivsync xcihref xcipclk xciydata[7:0] xcicdata[7:0] chip io camera i/f camera no skew no skew no skew figure 21-4. io connection guide 8-bit mode in this case, camera data are fed into S3C24A0 th rough only xciydata[7:0]. therefore, signal levels of xcicdata[7:0] are determined in appropriate value to prevent leakage current. if you connect these signals to ground, internal pull-up must be disabled at both normal and power saving mode. 16-bit mode in this case, camera data are fed into S3C24A0 th rough xciydata[7:0] for y and xcicdata[7:0] for cbcr.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-6 camera interface operation two dma ports camera interface has two dma ports. p-port(preview por t) and c-port(codec port) are separated from each other on ahb bus. at the view of system bus, two ports are independent. the p-port stores the rgb image data into memory for pip. the c-port stores the ycbcr 4:2:0 or 4:2:2 image data into memory for codec as mpeg-4, h.263, etc. these two master ports support the variable applic ations like dsc (digital steel camera), mpeg-4 video conference, video recording, etc. for example, p-port image can be used as preview image, and c-port image can be used as jpeg image in dsc application. also, the p-port or c-port can be disabled separately. camif external camera processor frame memory (sdram) p-port c-port itu format pip rgb codec image ycbcr 4:2:0 or ycbcr 4:2:2 camif external camera processor frame memory (sdram) p-port c-port itu format pip rgb codec image ycbcr 4:2:0 or ycbcr 4:2:2 window cut figure 21-7. two dma ports
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-7 clock domain camera interface has two clock domains. the one is the system bus clock, which is hclk. the other is the pixel clock, which is xcipclk. the system clock must be faster than pixel clock . as shown in figure 21-8, xciclk must be divided from the fixed frequency like usb pll clock. if ex ternal clock oscillator were used, xciclk should be floated. the clock for internal scaler is system clock. it is not necessary that two clock domains are synchronized to each other. other signals as xcipclk should be connected similarly to schmitt-triggered level shifter. xciclk divide counter 1/1,1/2,1/ 3...~1/16 upll external camera processor xcipclk S3C24A0 camera interface usb pll 96 mhz f usb /d f usb mpll variable freq. divide counter f mpll /d f mpll hclk external mclk normally use schmitt-triggered level-shifter figure 21-8. clock generation
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-8 frame memory hirerarchy frame memories consist of four ping-pong memories for each p- and c-ports. c-port ping-pong memories have three element memories that are luminance y, chrominance cb, and chrominance cr. c-port y 1 c-port cb 1 c-port cr 1 c-port y 2 c-port cb 2 c-port cr 2 c-port y 3 c-port cb 3 c-port cr 3 c-port y 4 c-port cb 4 c-port cr 4 p-port rgb 1 p-port rgb 2 p-port rgb 3 p-port rgb 4 4-pingpong frame memory (sdram) itu-601/656 ycbcr 4:2:2 8-bits camera interface ahb bus & memorycontroller p-port rgb 4:4:4 c-port 4:2:0,2 figure 21-9. ping-pong memory hierarchy
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-9 memory storing method the storing method to the frame memory is the little-endian method in codec path. the first entering pixels stored into lsb sides, and the last entering pixels stored into msb sides. the carried data by ahb bus is 32-bit word. so, camera interface stores the each y-cb-cr words by li ttle endian style. for preview path, two different formats exist. one pixel (color 1 pixel) is in one word for rg b 24-bit format. otherwise, two pixels are in one word for rgb 16-bit format. refer to figure 21-10. camera interface xcipclk xciydata[7:0] itu-601/656 ycbcr 4:2:2 8-bit input timing time y1 cb1 y2 cr1 y3 cb2 y4 cr2 cb frame memory cb4 cb3 cb2 cb1 cb8 cb7 cb6 cb5 little endian method cr frame memory cr4 cr3 cr2 cr1 cr8 cr7 cr6 cr5 little endian method rgb frame memory (16-bit) rgb2/1 rgb4/3 rgb6/5 rgb8/7 rgb10/9 rgb12/11 rgb14/13 rgb16/15 2 32-bit 1 r 5 g 6 b 5 16-bit rgb frame memory (24-bit) rgb1 rgb2 rgb3 rgb4 rgb5 rgb6 rgb7 rgb8 32-bit r g b y frame memory little endian method y4 y3 y2 y1 y8 y7 y6 y5 figure 21-10. memory storing style
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-10 timing diagram for register setting the first register setting for frame capture command can be occurred in anywhere of frame period. but, it is recommend to do first setting at the vsync ?l? state. vsy nc information can be read from status sfr. all command include imgcpten, is valid at vsync falling edge. be sure that except first sfr setting, all command should be programmed in isr(interrupt service routine). it is not allowed for target size information to be changed during capturing operation. howe ver, image mirror or rotation, windowing, and zoom in settings are allowed to change in capturing operation. xcivsync xcihref interrupt sfr setting (imgcpten) multi frame capturing reserved image capture < frame capture start > xcivsync xcihref interrupt new sfr command in capturing reserved image capture < new command valid timing diagram > new command figure 21-11. timing diagram for register setting note : fifo overflow of codec port will be set if codec port is not operating when preview port is operated. if you want to use codec port under this case, you should stop previe w port and reset camif using swrst bit of cigctrl register. then clear overflow of codec port and set special function registers that you want. overflow that doesn?t affect normal operation will be set when camera module is turned on and 31th bit of cisrcfmt is ?0?. we recommend that you set 31th bit of cisrcfmt to ?1? before camera module is turned on if
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-11 you use itu-r 601 format. if overflow is set before starting capturing, please clear overflow using clearing bits of ciwdofst. timing diagram for last irq irq except lastirq is generated before image capturi ng. last irq which means capture-end can be set by following timing diagram. lastirqen is auto-cleared and ,a s mentioned, sfr setting in isr is for next frame command. so, for adequate last irq, you should follow next sequence between lastirqen and imgcpten/imgcpten_cosc/im gcptenprsc. it is recommended that imgcpten/imgcpte n_cosc/imgcptenprsc are set at same time and at last of sfr setting in isr. framecnt which is read in isr, means next frame count. on following diagram, last captured frame count is ?1?. t hat is, frame 1 is the last-captured frame among frame 0~3. framecnt is increased by 1 at irq rising. vsync isr region imgcpten lastirqen capture o capture o capture o capture x irq auto cleared last irq isr region isr region isr region framecnt 01 23 3 figure 21-12. timing diagram for last irq
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-12 software interface camera interface sfr (special function register) camera interface special registers source format register register address r/w description reset value cisrcfmt 0x48000000 rw input source format 0 cisrcfmt bit description initial state itu601_656n [31] 1 : itu-r bt.601 ycbcr 8/16-bit mode enable 0 : itu-r bt.656 ycbcr 8-bit mode enable 0 uvoffset [30] cb,cr value offset control. 1 : +128 0 : +0 (normally used) 0 in16bit [29] itu-r bt 601 ycbcr 16-bit mode enable 0 sourcehsize [28:16] source horizontal pixel number (must be 8?s multiple) 0 order422 [15:14] input ycbcr order inform for input 8/16-bit mode 8-bit mode (in16bit = 0) 16-bit mode (in16bit = 1) 00 : ycbycr 01 : ycrycb 10 : cbycry 11 : crycby 00 : y y y y cbcrcbcr 01 : y y y y crcbcrcb others : forbidden 0 sourcevsize [12:0] source vertical pixel number (must be 16?s multiple for jpeg dct.) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-13 window option register register address r/w description reset value ciwdofst 0x48000 004 rw window offset register 0 sourcehsize sourcevsize original input window cut : winhorofst : winverofst targethsize_xx targetvsize_xx targethsize_xx = targethsize_co or targethsize_pr figure 21-13 window offset scheme ciwdofst bit description initial state winofsen [31] 1 : window offset enable 0 : no offset 0 clrovcofiy [30] 1 : clear the overflow indication flag of input codec fifo y 0 : normal 0 winhorofst [26:16] window horizontal offset by pixel unit. (the size of offset must be multiple of 8) 0 clrovcoficb [15] 1 : clear the overflow indication flag of input codec fifo cb 0 : normal 0 clrovcoficr [14] 1 : clear the overflow indication flag of input codec fifo cr 0 : normal 0 clrovprficb [13] 1 : clear the overflow indication flag of input preview fifo cb 0 : normal 0 clrovprficr [12] 1 : clear the overflow indication flag of input preview fifo cr 0 : normal 0 winverofst [10:0] window vertical offset by pixel unit 0 clear bits should be set by zero after clearing the flags.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-14 global control register register address r/w description reset value cigctrl 0x48000008 rw global control register 0x20000000 cigctrl bit description initial state swrst [31] camera interface software reset 0 camrst [30] external camera processor reset or power down control 0 reserved [29] should be ?1?. 1 testpattern [28:27] this register should be set at only itu-t 601 8-bit mode. not allowed with input 16-bit mode or itu-t 656 mode. (max. 1280 x 1024) 00 : external camera processor input (normal) 01 : color bar test pattern 10 : horizontal increment test pattern 11 . vertical increment test pattern 0 invpolpclk [26] 1 : inverse the polarity of xcipclk 0 : normal(camera data is fetched at rising edge of xcipclk) 0 invpolvsync [25] 1 : inverse the polarity of xcivsync 0 : normal 0 invpolhref [24] 1 : inverse the polarity of xcihref 0 : normal 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-15 y1 start address register register address r/w description reset value cicoysa1 0x48000018 rw 1 st y frame start address for codec dma 0 cicoysa1 bit description initial state cicoysa1 [31:0] 1 st y frame start address for codec dma 0 y2 start address register register address r/w description reset value cicoysa2 0x4800001c rw 2 nd y frame start address for codec dma 0 cicoysa2 bit description initial state cicoysa2 [31:0] 2 nd y frame start address for codec dma 0 y3 start address register register address r/w description reset value cicoysa3 0x48000020 rw 3 rd y frame start address for codec dma 0 cicoysa3 bit description initial state cicoysa3 [31:0] 3 rd y frame start address for codec dma 0 y4 start address register register address r/w description reset value cicoysa4 0x48000024 rw 4 th y frame start address for codec dma 0 cicoysa4 bit description initial state cicoysa4 [31:0] 4 th y frame start address for codec dma 0 cb1 start address register register address r/w description reset value cicocbsa1 0x48000028 rw 1 st cb frame start address for codec dma 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-16 cicocbsa1 bit description initial state cicocbsa1 [31:0] 1 st cb frame start address for codec dma 0 cb2 start address register register address r/w description reset value cicocbsa2 0x4800002c rw 2 nd cb frame start address for codec dma 0 cicocbsa2 bit description initial state cicocbsa2 [31:0] 2 nd cb frame start address for codec dma 0 cb3 start address register register address r/w description reset value cicocbsa3 0x48000030 rw 3 rd cb frame start address for codec dma 0 cicocbsa3 bit description initial state cicocbsa3 [31:0] 3 rd cb frame start address for codec dma 0 cb4 start address register register address r/w description reset value cicocbsa4 0x48000034 rw 4 th cb frame start address for codec dma 0 cicocbsa4 bit description initial state cicocbsa4 [31:0] 4 th cb frame start address for codec dma 0 cr1 start address register register address r/w description reset value cicocrsa1 0x48000038 rw 1 st cr frame start address for codec dma 0 cicocrsa1 bit description initial state cicocrsa1 [31:0] 1 st cr frame start address for codec dma 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-17 cr2 start address register register address r/w description reset value cicocrsa2 0x4800003c rw 2 nd cr frame start address for codec dma 0 cicocrsa2 bit description initial state cicocrsa2 [31:0] 2 nd cr frame start address for codec dma 0 cr3 start address register register address r/w description reset value cicocrsa3 0x48000040 rw 3 rd cr frame start address for codec dma 0 cicocrsa3 bit description initial state cicocrsa3 [31:0] 3 rd cr frame start address for codec dma 0 cr4 start address register register address r/w description reset value cicocrsa4 0x48000044 rw 4 th cr frame start address for codec dma 0 cicocrsa4 bit description initial state cicocrsa4 [31:0] 4 th cr frame start address for codec dma 0 codec target format register register address r/w description reset value cicotrgfmt 0x48000048 rw target image format of codec dma 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-18 original image x-axis flip y-axis flip 180' rotation figure 21-14 image mirror and rotation cicotrgfmt bit description initial state in422_co [31] 1 : ycbcr 4:2:2 codec scaler input image format. 0 : ycbcr 4:2:0 codec scaler input image format. in this case, horizontal line decimation is performed before codec scaler. (normal) 0 out422_co [30] 1 : ycbcr 4:2:2 codec scaler output image format. this mode is mainly for s/w jpeg. 0 : ycbcr 4:2:0 codec scaler output image format. this mode is mainly for mpeg-4 codec and h/w jpeg dct.(normal) 0 targethsize_co [28:16] horizontal pixel number of target image for codec dma (16?s multiple) 0 flipmd_co [15:14] image mirror and rotation for codec dma 00 : normal 01 : x-axis mirror 10 : y-axis mirror 11 : 180rotation 0 targetvsize_co [12:0] vertical pixel number of target image for codec dma (must be 16?s multiple for jpeg dct.) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-19 codec dma control register register address r/w description reset value cicoctrl 0x4800004c rw codec dma control 0 cicoctrl bit description initial state yburst1_co [23:19] main burst length for codec y frames 0 yburst2_co [18:14] remained burst length for codec y frames 0 cburst1_co [13:9] main burst length for codec cb/cr frames 0 cburst2_co [8:4] remained burst length for codec cb/cr frames 0 lastirqen_co [2] 1 : enable last irq at the end of frame capture (it is recommended to check the done signal of capturing image for jpeg.) 0 : normal 0 all burst lengthes should be one of the 2,4,8,16. example 1. target image size : qcif (horizontal y width = 176) 176 / 4 = 44 word. 44 % 8 = 4 main burst = 8, remained burst = 4 example 2. target image size : vga (horizontal y width = 640) 640 / 4 = 160 word. 160 % 16 = 0 main burst = 16, remained burst = 16 example 3. target image size : qcif (horizontal c width = 88) 88 / 4 = 22 word. 22 % 4 = 2 main burst = 4, remained burst = 2 (htrans==incr) register setting guide for codec scaler and preview scaler src_width and dst_width satisfy the following constraints. in src_width case, the number of horizontal pixel can be represented to the power of 8. in dst_widt h case, the number of horizontal pixel can be represented kn where n = 1,2,3, ? and k = 2/4/16 for 24bpp rgb/16bpp rgb/ycbcr image, respectively. targethsize should not be larger than sourcehsize. similarly, ta rgetvsize should not be la rger than sourcevsize.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-20 sourcehsize sourcevsize targethsize_xx targetvsize_xx original input scale down sourcehsize sourcevsize original input zoom in : winhorofst : winverofst targethsize_xx targetvsize_xx src_width = sourcehsize src_height = sourcevsize targethsize_xx = targethsize_co or targethsize_pr dst_width = targethsize_xx dst_height = targetvsize_xx targethsize_xx = targethsize_co or targethsize_pr dst_width = targethsize_xx dst_height = targetvsize_xx src_width = sourcehsize - (2 x winhorofst) src_height = sourcevsize - (2 x winverofst) figure 21-15 scaling scheme the other control registers of pre-scaled image size, pre- scale ratio, pre-scale shift ratio and main scale ratio are defined according to the following equations. if ( src_width >= 64 dst_width ) { exit(-1); /* out of horizontal scale range */ } else if (src_width >= 32 dst_width) { prehorratio_xx = 32; h_shift = 5; } else if (src_width >= 16 dst_width) { prehorratio_xx = 16; h_shift = 4; } else if (src_width >= 8 dst_width) { prehorratio_xx = 8; h_shift = 3; } else if (src_width >= 4 dst_width) { prehorratio_xx = 4; h_shift = 2; } else if (src_width >= 2 dst_width) { prehorratio_xx = 2; h_shift = 1; } else { prehorratio_xx = 1; h_shift = 0; } predstwidth_xx = src_width / prehorratio_xx; mainhorratio_xx = ( src_width << 8 ) / ( dst_width << h_shift); if ( src_height >= 64 dst_height ) { exit(-1); /* out of vertical scale range */ } else if (src_height >= 32 dst_height) { preverratio_xx = 32; v_shift = 5; } else if (src_height >= 16 dst_height) { preverratio_xx = 16; v_shift = 4; }
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-21 else if (src_height >= 8 dst_height) { preverratio_xx = 8; v_shift = 3; } else if (src_height >= 4 dst_height) { preverratio_xx = 4; v_shift = 2; } else if (src_height >= 2 dst_height) { preverratio_xx = 2; v_shift = 1; } else { preverratio_xx = 1; v_shift = 0; } predstheight_xx = src_height / preverratio_xx; mainverratio_xx = ( src_height << 8 ) / ( dst_height << v_shift); shfactor_xx = 10 ? ( h_shit + v_shift); note: in preview path, pre-scaled h_width must be the less than 640. (the maximum size of preview path horizontal line buffer is 640.)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-22 codec pre-scaler control register 1 register address r/w description reset value cicoscpreratio 0x48000050 rw codec pre-scaler ratio control 0 cicoscpreratio bit description initial state shfactor_co [31:28] shift factor for codec pre-scaler 0 prehorratio_co [22:16] horizontal ratio of codec pre-scaler 0 preverratio_co [6:0] vertical ratio of codec pre-scaler 0 codec pre-scaler control register 2 register address r/w description reset value cicoscpredst 0x48000054 rw codec pre-scaler destination format 0 cicoscpredst bit description initial state predstwidth_co [27:16] destination width for codec pre-scaler 0 predstheight_co [11:0] destination height for codec pre-scaler 0 codec main-scaler control register register address r/w description reset value cicoscctrl 0x48000058 rw codec main-scaler control 0 cicoscctrl bit description initial state scalerbypass_co [31] codec scaler bypass for upper 2048 x 2048 size (in this case, imgcpten_cosc and imgcpten_prsc should be 0, but imgcpten should be 1. it is not allowed to capturing preview image. this mode is intended to capture jpeg input image for dsc application) in this case, input pixel buffering depends on only input fifos, so system bus should be not busy in this mode. 0 scaleupdown_co [30:29] scale up/down flag for codec scaler(in 1:1 scale ratio, this bit should be ?1?) 00 = down 11 = up 00 mainhorratio_co [24:16] horizontal scale ratio for codec main-scaler 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-23 coscalerstart [15] codec scaler start 0 mainverratio_co [8:0] vertical scale ratio for codec main-scaler 0 codec dma target area register register address r/w description reset value cicotarea 0x4800005c rw codec pre-scaler destination format 0 cicotarea bit description initial state cicotarea [25:0] target area for codec dma = target h size x target v size 0 codec status register register address r/w description reset value cicostatus 0x48000064 r codec path status 0 cicostatus bit description initial state ovfiy_co [31] overflow state of codec fifo y 0 ovficb_co [30] overflow state of codec fifo cb 0 ovficr_co [29] overflow state of codec fifo cr 0 vsync [28] camera vsync (this bit can be referred by cpu for first sfr setting after external camera muxing. and, it can be seen in the itu-r bt 656 mode) 1:blank, 0: field 0 framecnt_co [27:26] frame count of codec dma (thi s counter value means the next frame number) 0 winofsten_co [25] window offset enable status 0 flipmd_co [24:23] flip mode of codec dma 0 imgcpten_camif [22] image capture enable of camera interface 0 imgcpten_cosc [21] image capture enable of codec path 0 vsync_e [20] status of signal level of xcivsync x
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-24 rgb1 start address register register address r/w description reset value ciprclrsa 1 0x4800006c rw 1 st rgb frame start address for preview dma 0 ciprclrsa1 bit description initial state ciprclrsa1 [31:0] 1 st rgb frame start address for preview dma 0 rgb2 start address register register address r/w description reset value ciprclrsa 2 0x48000070 rw 2 nd rgb frame start address for preview dma 0 ciprclrsa2 bit description initial state ciprclrsa2 [31:0] 2 nd rgb frame start address for preview dma 0 rgb3 start address register register address r/w description reset value ciprclrsa 3 0x48000074 rw 3 rd rgb frame start address for preview dma 0 ciprclrsa3 bit description initial state ciprclrsa3 [31:0] 3 rd rgb frame start address for preview dma 0 rgb4 start address register register address r/w description reset value ciprclrsa 4 0x48000078 rw 4 th rgb frame start address for preview dma 0 ciprclrsa4 bit description initial state ciprclrsa4 [31:0] 4 th rgb frame start address for preview dma 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-25 preview target format register register address r/w description reset value ciprtrgfmt 0x4800007c rw target im age format of preview dma 0 ciprtrgfmt bit description initial state targethsize_pr [28:16] horizontal pixel number of target image for preview dma . 16bpp rgb : 4n(n=1,2,3, ?) 24bpp rgb : 2n(n=1,2,3, ?) 0 flipmd_pr [15:14] image mirror and rotation for preview dma 00 : normal 01 : x-axis mirror 10 : y-axis mirror 11 : 180 rotation 0 targetvsize_pr [12:0] vertical pixel num ber of target image for preview dma 0 preview dma control register register address r/w description reset value ciprctrl 0x48000080 rw preview dma control related 0 ciprctrl bit description initial state rgbburst1_pr [23:19] main burst length for preview rgb frames 0 rgbburst2_pr [18:14] remained burst length for preview rgb frames 0 lastirqen_pr [2] 1 : enable last irq at the end of frame capture 0 : normal 0 all burst lengths must be one of the 2,4,8,16. example 1. target image size : qcif for rgb 32-bit fo rmat (horizontal width = 176 pixels. 1 pixel = 1 word) 176 pixel = 176 word. 176 % 16 = 0 main burst = 16, remained burst = 16 example 2. target image size : vga for rgb 16-bit form at (horizontal width = 640 pixels. 2 pixel = 1 word) 640 / 2 = 320 word.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-26 160 % 16 = 0 main burst = 16, remained burst = 16 note: preview path contains 640 pixel line buffer.(codec path contains 2048 pixel line buffer) so, upper 1280 pixels, input images must be pre-scaled by over 1/2 for capturing valid preview image. preview pre-scaler control register 1 register address r/w description reset value ciprscpreratio 0x48000084 rw preview pre-scaler ratio control 0 ciprscpreratio bit description initial state shfactor_pr [31:28] shift factor for preview pre-scaler 0 prehorratio_pr [22:16] horizontal ratio of preview pre-scaler 0 preverratio_pr [6:0] vertical ratio of preview pre-scaler 0 preview pre-scaler control register 2 register address r/w description reset value ciprscpredst 0x48000088 rw preview pre-scaler destination format 0 ciprscpredst bit description initial state predstwidth_pr [27:16] destination width for preview pre-scaler 0 predstheight_pr [11:0] destination height for preview pre-scaler 0 preview main-scaler control register register address r/w description reset value ciprscctrl 0x4800008c rw preview main-scaler control 0 ciprscctrl bit description initial state sample_pr [31] sampling method for format conversion. (normally 1) 0 rgbformat_pr [30] 1 : 24-bit rgb , 0 : 16-bit rgb 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 2 1-27 scaleupdown_pr [29:28] scale up/down flag for preview scaler(in 1:1 scale ratio, this bit should be ?1?) 00 = down 11 = up 00 mainhorratio_pr [24:16] horizontal scale ratio for preview main-scaler 0 prscalerstart [15] preview scaler start 0 mainverratio_pr [8:0] vertical scale ratio for preview main-scaler 0 preview dma target area register register address r/w description reset value ciprtarea 0x48000090 rw preview pre-scaler destination format 0 ciprtarea bit description initial state ciprtarea [25:0] target area for preview dma = target h size x target v size 0 preview status register register address r/w description reset value ciprstatus 0x48000098 r preview path status 0 ciprstatus bit description initial state ovficb_pr [31] overflow state of preview fifo cb 0 ovficr_pr [30] overflow state of preview fifo cr 0 framecnt_pr [27:26] frame count of preview dma 0 flipmd_pr [24:23] flip mode of preview dma 0 imgcpten_prsc [21] image capture enable of preview path 0 image capture enable register register address r/w description reset value ciimgcpt 0x480000a0 rw image capture enable command 0 ciimgcpt bit description initial state
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor camera interface 21-28 imgcpten [31] camera interface global capture enable 0 imgcpten_cosc [30] capture enable for codec scaler. this bit must be zero in scaler- bypass mode. 0 imgcpten_prsc [29] capture enable for preview scaler. this bit must be zero in scaler- bypass mode. 0 note: this register must be set at last. notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 video codec 22 -1 mpeg-4 video codec overview mpeg-4 is an iso/iec standard developed by mpeg (mov ing picture experts group). mpeg-4 video aims at providing standardized core technologies allowing efficient storage, transmission and manipulation of video data in multimedia environments. mpeg-4 video codec of S3C24A0 provides high performance solution and lower the processing load of embedded processor core. the processing clock for dct/quantization and motion estimation can be controlled by embedded processor core to reduce the power consumption. feature - iso/iec mpeg-4 simple profile @ level 3 / itu-t h.263 base line - amba ahb interface - real-time encoding / decoding - scalable image size : m x n macro-blocks up to 2048x2048 - hardware accelerator for motion estimation, motion compensation, dct/quantization and vlc/vld - unrestricted mode & advanced prediction mode (4mv) - half-pel search - programmable processing clock in dct/quantization and motion estimation : hclk ~ hclk/30
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 video codec S3C24A0 risc microprocessor 22-2 block diagram figure 22-1 shows the functional block diagram of s3 c24a0 mpeg-4 video codec. this codec consists of four parts, i.e., dct/quantization, motion c ompensation, motion estimation and vlx(vlc/vld). curr mem dct mced mem q iq idct recon mem qp factor coef mem sdram sdram sdram me prev mem curr mem mc dct/q vlx figure 22-1. mpeg-4 video codec block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion estimation 23-1 mpeg-4 motion estimation overview the mpeg-4 motion estimation block is a part of mpeg-4 video codec. motion estimation is an essential part in standard video coder such as h.26x, mpeg-1, mpeg-2 and mpeg-4. by removing temporal redundancies exiting in adjacent frames advanced mrmcs (multi-resolution search using multiple candidates and spatial correlation of motion field) algorithm is applied and it is based on the hierarchical search block-matching algorithm. feature - mpeg-4 simple profile @ level 3 / h.263 base line - amba ahb interface - using advanced mrmcs (multi-resolution search using multiple candidates and spatial correlation of motion field) algorithm - scalable image size : m x n macro-blocks up to 2048x2048 - unrestricted mode & advanced prediction mode (4mv) - intra / inter mode decision - macroblock-based padding - search range : [-16, 15.5] - half-pel search - double buffering of frame data - re-use of overlapped search range data - variable processing clock ( hclk ~ hclk / 30 )
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion estimation S3C24A0 risc microprocessor 23-2 mpeg-4 motion estimation operation block diagram figure 23-1 shows the functional block diagram of mpeg-4 motion estimation. this block includes two parts with different clocks, i.e., system clock part and motion estimation clock part. config sdram_ctrl sdram_read sram_write internal_ctrl interpolation data_arrange prev_mem (80x64x12) curr_mem (16x16x8x2) bsu candidate shift_reg sram_read mode decision system clock part me clock part figure 23-1. mpeg-4 motion estimation block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion estimation 23-3 operation flow - firstly, set current, previous, and motion vector start address registers. - start address of previous frame must be considered the padding area. - set command register to operate motion estimation block. - current image data and padded previous image data of a macro-block are stored into the internal sram buffers from the external sdram. - operations to find motion vector of each macro-block are started after data transfer. - after the completion of searches for each macro-block, the result data is written into the external sdram and then operations for one macro-block are finished. - the operation unit in command register is set to decide the number of the macro-block to operate motion estimation continuously. yimage current frame start address yimage previous frame start address offset (a) current frame (b) previous frame figure 23-2. memory map of y (luminance) image for current and previous frames table 1. example of sizes of y image and offset for qcif and cif image format qcif cif current frame 176x144 = 25,344 352x288 = 101,376 y image previous frame (176+16x2)x(144+16x2) = 36,608 (352+16x2)x(288+16x2) =122,880 offset (176+16x2)x16+16 = 3,344 (352+16x2)x16+16 = 6,160
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion estimation S3C24A0 risc microprocessor 23-4 result data - the result of the motion estimation for each macro-block is stored into the external sdram area assigned in motion vector start address register. - the result data of each macro-block is as follows. address 0 1 2 3 4 (a) location of 8x8 block in one macro-block (b) result data of one macro-block figure 23-3. motion estimation result data - mvx0, 1, 2, 3 and mvy0, 1, 2, 3 are x and y components for motion vector of block 0, 1, 2, 3, respectively. - the value of bit 0 of mvx0, 1, 2, 3 and mvy0, 1, 2, 3 indicates the value of half-pel unit. if this bit is 1, the value is 0.5. otherwise, it indicates 0.0. bit [7:1] is the signed number that is represented using 2?s complement system. for example, if values of mvx0 and mvy0 are 0xe2 and 0x1b, respectively, the values of x and y components of motion vector are ?15.0 and 13.5, respectively. - in the case of 4mv mode, motion vectors of 4 blocks are generated and in other cases, 4 motion vectors have the same value. - sad0, 1, 2 and 3 are the sad values for each block and they can be used for dct/q skipping. - the value of intra/inter mode indicates t hat 0x0000 is inter mode and 0xffff is intra mode. this value is only valid in case of mpeg-4 mode and always is 0x0000, that is, inter mode in h.263 mode. - sadinter is the result of min { sad16, sad8 } afte r half-pel operation and it is used for intra/inter mode decision. block 0 block 1 block 2 block 3 mvy1 mvx1 mvy0 mvx0 mvy3 mvx3 mvy2 mvx2 sad1 sad0 sad3 sad2 sadinter intra/inter mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion estimation 23-5 mpeg-4 motion estimation special registers current frame start address register (me_cfsa) register address r/w description reset value me_cfsa 0x4880_0000 r/w current frame start address register 0x0000_0000 me_cfsa bit description initial state current frame start address [31:0] set current frame start address 0x0000_0000 note 1. current frame start address is the start address of current y image. motion estimation operates only for y (luminance) image. previous frame start address register (me_pfsa) register address r/w description reset value me_pfsa 0x4880_0004 r/w previous frame start address register 0x0000_0000 me_pfsa bit description initial state previous frame start address [31:0] set previous frame start address 0x0000_0000 note 1. previous frame start address is the start address of previous y image. motion estimation operates only for y (luminance) image. 2. previous frame start address must be considered the padding area and it is the start address of the original previous image except the padding area. motion vector start address register (me_mvsa) register address r/w description reset value me_mvsa 0x4880_0008 r/w motion vector start address register 0x0000_0000 me_mvsa bit description initial state motion vector start address [31:0] set motion vector start address 0x0000_0000 note 1. motion vector start address is the start address to store the result data of motion estimation. 2. the number of the result data is determined according to the operation unit of command register.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion estimation S3C24A0 risc microprocessor 23-6 command register (me_cmnd) register address r/w description reset value me_cmnd 0x4880_000c r/w command register 0x0000_0001 me_cmnd bit description initial state - [31:18] reserved 0x0 round control bit [17] 0 : round bit 0 1 : round bit 1 0 4mv mode enable [16] 0 : 16x16 prediction mode 1 : advanced prediction mode (4mv) 0 - [15:4] reserved 0x0 me operation start bit [3] 0 : not active 1 : enable 0 mpeg-4/h.263 mode select [2] 0 : mpeg-4 mode 1 : h.263 mode 0 frame start bit [1] 0 : not active 1 : enable 0 interrupt request clear bit [0] 0 : not active 1 : clear 1 note 1. frame start bit is enabled only when the first start of the frame. 2. me operation start bit is enable every operation unit in the frame. 3. interrupt request clear bit is cleared when me operation start bit is enable at the same time.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion estimation 23-7 status & s/w reset register (me_stat_swr) register address r/w description reset value me_stat_swr 0x4880_0010 r/(w) status & s/w reset register 0x0000_0002 me_stat_swr bit description initial state reserved [31:20] r reserved 0x0 bsu state buf fsm [19:16] r bsu state buf fsm in candidate block 0x0 data flow fsm [15:12] r data flow fsm in internal_ctrl block 0x0 bsu fsm [11:8] r bsu fsm in internal_ctrl block 0x0 reserved [7] r reserved 0 control fsm [6:4] r control fsm in sdram_ctrl block 0x0 reserved [3:2] r reserved 0x0 s/w reset bit [1] r/w 0 : set s/w reset 1 : clear s/w reset 1 motion estimation status bit [0] r 0 : idle 1 : busy 0 note 1. in case of not using interrupt, motion estimation operation must be started when motion estimation status bit is ?0?. 2. s/w reset bit is used to reset motion estimation block. it reset special registers and internal finite state machines. 3. since s/w reset bit keeps the written value until written into ?0? or hardware reset, be careful to use s/w reset bit.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion estimation S3C24A0 risc microprocessor 23-8 configuration register (me_cnfg) register address r/w description reset value me_cnfg 0x4880_0014 r/w configuration register 0x0010_0063 me_cnfg bit description initial state - [31:25] reserved 0x0 fast mode enable bit [24] 0 : disable 1 : enable 0 - [23] reserved 0 threshold value [22:16] threshold value to be compared to the intensity variation in the fast mode 0x10 - [15:14] reserved 0x0 operation unit [13:0] the number of macro-blocks to operate motion estimation continuously 0x0063 note 1. the operation unit is variable only inside one frame. 2. in fast mode, the execution time is considerably reduced with less psnr. 3. fast mode enable bit is only valid in case of mpeg-4 mode. in h.263 mode, this bit always is not enabled. image format register (me_imgfmt) register address r/w description reset value me_imgfmt 0x4880_0018 r/w image format register 0x0000_080a me_imgfmt bit description initial state - [31:15] reserved 0x0 n value [14:8] the number of vertical macro-blocks minus one 0x08 -[7]reserved 0 m value [6:0] the number of horizontal macro-blocks minus one 0x0a
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion compensation 24-1 mpeg-4 motion compensation overview the mpeg-4 motion compensation block is a part of mpeg-4 video codec. motion compensation is a key element in the inter compression. in inter compression pixels in a region of a previous frame are used to predict pixels in a region of the current frame. differences between the previous frame and the mced frame are then coded to whatever accuracy is affordable at the desired bit-rate. feature - mpeg-4 simple profile @ level 3 / h.263 base line - amba ahb interface - 8x8 block-based motion compensation - scalable image size : m x n macro-blocks up to 2048x2048 - dedicated dma - unrestricted mode & advanced prediction mode (4mv) - search range : [-32, 31.5] - half-pel search - error concealment support - encoding / decoding
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion compensation S3C24A0 risc microprocessor 24-2 mpeg-4 motion compensation operation block diagram figure 24-1 shows the functional block diagram of mpeg-4 motion compensation. regs addr_gen motionvector fifo control figure 24-1. mpeg-4 motion compensation block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion compensation 24-3 operation flow - firstly, set y/cb/cr start address registers of current and previous. each start address of current and previous frames must be considered the padding area. - secondly, set motion vector start address register. - set command register to operate motion compensation block. - the operation unit in command register is set to decide the number of the macro-block to motion compensation continuously. - the operation of motion compensation is as follows. start -> motion vector read -> data read -> data processing -> data write - motion compensation is operated in 8x8 block unit. - motion compensation cannot support the encoding and the decoding at the same time. - current and previous frame are padded frames. yimage cb image cr image original frame y start address original frame cb start address original frame cr start address yimage cb image cr image padded frame y start address y offset cb offset cr offset padded frame cb start address padded frame cr start address (a) original frame (b) padded frame figure 24-2. y/cb/cr image memory map of original and padded frames table 1. sizes of y/cb/cr image and offset for qcif and cif qcif cif y 176x144 = 25,344 352x288 = 101,376 original frame cb/cr 88x72 = 6,336 176x144 = 25,344 y (176+16x2)x(144+16x2) = 36,608 (352+16x2)x(288+16x2) = 122,880 padded frame cb/cr (88+8x2)x(72+8x2) = 9,152 (176+8x2)x(144+8x2) = 30,720 y (176+16x2)x16+16 = 3,344 (352+16x2)x16+16 = 6,160 offset cb/cr (88+8x2)x8+8 = 840 (176+8x2)x8+8 = 1,544
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion compensation S3C24A0 risc microprocessor 24-4 configuration of qcif / cif frame figure 24-3. y/cb/cr configurati on for qcif/cif original frame figure 24-4. y/cb/cr configurat ion for qcif/cif padded frame qcif y 176 144 176 + 32 = 208 144 + 32 = 176 qcif cb/cr 88 72 88 + 16 = 104 72 + 16 = 88 cif y 352 288 352 + 32 = 384 288 + 32 = 320 cif cb/cr 176 144 176 + 16 = 192 144 + 16 = 160 qcif mv 32-bit 5 x 99 = 495 cif mv 32-bit 5 x 396 = 1980 qcif y 144 qcif cb/cr 72 176 88 cif y 288 cif cb/cr 144 352 176
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion compensation 24-5 figure 24-5. motion vector conf iguration for qcif/cif image mpeg-4 motion compensation special registers previous frame y start address regist er for the encoder (mc_pfysa_enc) register address r/w description reset value mc_pfysa_enc 0x48c0_0000 r/w previous fram e y start address register (enc) 0x0000_0000 mc_pfysa_enc bit description initial state previous frame y start address (enc) [31:0] set previous frame y start address (enc) 0x0000_0000 mced frame y start address register for the encoder (mc_mfysa_enc) register address r/w description reset value mc_mfysa_enc 0x48c0_0004 r/w mced frame y start address register (enc) 0x0000_0000 mc_mfysa_enc bit description initial state mced frame y start address (enc) [31:0] set mced frame y start address (enc) 0x0000_0000 previous frame y start address regist er for the decoder (mc_pfysa_dec) register address r/w description reset value mc_pfysa_dec 0x48c0_0008 r/w previous frame y start address register (dec) 0x0000_0000 mc_pfysa_dec bit description initial state previous frame y start address (dec) [31:0] set previous frame y start address (dec) 0x0000_0000 mced frame y start address register for the decoder (mc_mfysa_dec) register address r/w description reset value mc_mfysa_dec 0x48c0_000c r/w mced frame y start address register (dec) 0x0000_0000 mc_mfysa_dec bit description initial state mced frame y start address (dec) [31:0] set mced frame y start address (dec) 0x0000_0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion compensation S3C24A0 risc microprocessor 24-6 previous frame cb start address regist er for the encoder (mc_pfcbsa_enc) register address r/w description reset value mc_pfcbsa_enc 0x48c0_0010 r/w previous frame cb start address register (enc) 0x0000_0000 mc_pfcbsa_enc bit description initial state previous frame cb start address (enc) [31:0] set previous frame cb start address (enc) 0x0000_0000 previous frame cr start address regist er for the encoder (mc_pfcrsa_enc) register address r/w description reset value mc_pfcrsa_enc 0x48c0_0014 r/w previous frame cr start address register (enc) 0x0000_0000 mc_pfcrsa_enc bit description initial state previous frame cr start address (enc) [31:0] set previous frame cr start address (enc) 0x0000_0000 mced frame cb start address register for the encoder (mc_mfcbsa_enc) register address r/w description reset value mc_mfcbsa_enc 0x48c0_0018 r/w mced frame cb start address register (enc) 0x0000_0000 mc_mfcbsa_enc bit description initial state mced frame cb start address (enc) [31:0] set mced frame cb start address (enc) 0x0000_0000 mced frame cr start address register for the encoder (mc_mfcrsa_enc) register address r/w description reset value mc_mfcrsa_enc 0x48c0_001c r/w mced frame cr start address register (enc) 0x0000_0000 mc_mfcrsa_enc bit description initial state mced frame cr start address (enc) [31:0] set mced frame cr start address (enc) 0x0000_0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion compensation 24-7 previous frame cb start address regist er for the decoder (mc_pfcbsa_dec) register address r/w description reset value mc_pfcbsa_dec 0x48c0_0020 r/w previous frame cb start address register (dec) 0x0000_0000 mc_pfcbsa_dec bit description initial state previous frame cb start address (dec) [31:0] set previous frame cb start address (dec) 0x0000_0000 previous frame cr start address regist er for the decoder (mc_pfcrsa_dec) register address r/w description reset value mc_pfcrsa_dec 0x48c0_0024 r/w previous frame cr start address register (dec) 0x0000_0000 mc_pfcrsa_dec bit description initial state previous frame cr start address (dec) [31:0] set previous frame cr start address (dec) 0x0000_0000 mced frame cb start address register for the decoder (mc_mfcbsa_dec) register address r/w description reset value mc_mfcbsa_dec 0x48c0_0028 r/w mced frame cb start address register (dec) 0x0000_0000 mc_mfcbsa_dec bit description initial state mced frame cb start address (dec) [31:0] set mced frame cb start address (dec) 0x0000_0000 mced frame cr start address register for the decoder (mc_mfcrsa_dec) register address r/w description reset value mc_mfcrsa_dec 0x48c0_002c r/w mced frame cr start address register (dec) 0x0000_0000 mc_mfcrsa_dec bit description initial state mced frame cr start address (dec) [31:0] set mced frame cr start address (dec) 0x0000_0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion compensation S3C24A0 risc microprocessor 24-8 motion vector start address regist er for the encoder (mc_mvsa_enc) register address r/w description reset value mc_mvsa_enc 0x48c0_0030 r/w motion vector start address register (enc) 0x0000_0000 mc_mvsa_enc bit description initial state motion vector start address (enc) [31:0] set motion vector start address (enc) 0x0000_0000 motion vector start address regist er for the decoder (mc_mvsa_dec) register address r/w description reset value mc_mvsa_dec 0x48c0_0034 r/w motion vector start address register (dec) 0x0000_0000 mc_mvsa_dec bit description initial state motion vector start address (dec) [31:0] set motion vector start address (dec) 0x0000_0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion compensation 24-9 command register (mc_cmnd) register address r/w description reset value mc_cmnd 0x48c0_0038 r/w command register 0x0000_0040 mc_cmnd bit description initial state - [31:18] reserved 0x0 rounding control bit [17] 0 : round bit 0 1 : round bit 1 0 - [16:7] reserved 0x0 encoder / decoder mode select [6] 0 : decoder 1 : encoder 1 interrupt request clear bit [5] 0 : not active 1 : enable 0 mc operation start bit [4] 0 : not active 1 : enable 0 - [3:2] reserved 0x0 mc abort bit [1] 0 : not active 1 : enable 0 - [0] reserved 0 note 1. mc operation start bit is enabled every operation unit in the frame. 2. interrupt request clear bit is cleared when mc operation start bit is enabled at the same time. 3. mc abort bit has the same function as s/w reset bit of status & s/w reset register and is cleared automatically.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion compensation S3C24A0 risc microprocessor 24-10 status & s/w reset re gister (mc_stat_swr) register address r/w description reset value mc_stat_swr 0x48c0_003c r/(w) status & s/w reset register 0x0000_0002 mc_stat_swr bit description initial state - [31:9] r reserved 0x0 control fsm [8:4] r control fsm in control block 0x0 - [3:2] r reserved 0x0 s/w reset bit [1] r/w 0 : set s/w reset 1 : clear s/w reset 1 motion compensation status bit [0] r 0 : idle 1 : busy 0 note 1. in case of not using interrupt, motion compensation operation must be started when motion compensation status bit is ?0?. 2. s/w reset bit is used to reset motion compensation block. it reset special registers and internal finite state machines. 3. since s/w reset bit keeps the written value until written into ?0? or hardware reset, be careful to use s/w reset bit.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 motion compensation 24-11 configuration register (mc_cnfg) register address r/w description reset value mc_cnfg 0x48c0_0040 r/w configuration register 0x0000_0063 mc_cnfg bit description initial state mc x, y count update enable bit [31] 0 : disable 1 : enable 0 mc y count update value [30:24] update value when bit 31 is set to ?1? 0x0 - [23] reserved 0 mc x count update value [22:16] update value when bit 31 is set to ?1? 0x0 - [15:14] reserved 0x0 operation unit [13:0] the number of the macro-block to operate motion compensation continuously 0x0063 note 1. the operation unit is variable only inside one frame. 2. mc x, y count update enable bit and mc x, y count update value should be written at the same time to operate motion compensation for specific macro-blocks in the frame..
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. mpeg-4 motion compensation S3C24A0 risc microprocessor 24-12 image format register (mc_imgfmt) register address r/w description reset value mc_imgfmt 0x48c0_0044 r/w image format register 0x0000_080a me_imgfmt bit description initial state - [31:15] reserved 0x0 n value [14:8] the number of vertical macro-blocks minus one 0x08 - [7] reserved 0 m value [6:0] the number of horizontal macro-blocks minus one 0x0a
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -1 mpeg-4 dctq (preliminary) overview this specification defines the dct, idct, quantisation and dequantisation engine for mpeg-4 codec (refer figure 25-1). mpeg-4 dctq engine gets current macroblo ck, previous macroblock and quantisation information from main memory. after internal dctq operation, this engine writes quantized coefficients and reconstructed macroblock to main memory. using quantisation factor, it is possible to control bit-rate for video streams. padding operation for motion estimation supports on the writing reconstruction macroblock. also, it is possible to setting intra or inter mode and qp value with accessing quantisation information in memory. this engine has own dma module. so, just by setting function attributes into dctq sfr (special function register), this engine automatically performs dct, idct, quantisation, dequantisation, and memory access. current mb local mem. dct q level local mem. iq idct q-inform reconstruct mb local mem. sdram reference mb local mem. mc me mpeg-4 dctq sdram sdram sdram sdram q/iq skip mode figure 25-1. dctq overview
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25-2 features ? h.263, mpeg-4 simple profile level 0,1,2 3 supports. ? dct / idct / q / iq operations ? residual extraction / image reconstruction ? padding operation for unrestricted motion compensation ? rate control by q-inform ? intra refresh feasibility by q-inform ? dedicated dma ? mpeg-4 encoder/decoder support ? jpeg dct/idct support ? variable aspect ratio and size (up to 4096 x 4096) timing diagram dctq ip operates by opunit. opunit is a macroblock-based, which is 16x16 pixel array. one macroblock consists of six 8x8 block, whic h are 4 luminance blocks and, 2 chrominance blocks. dctq ip starts with dctq_start signal by register setting. and, during operation, dctq_busy signal remains high. after dctq operation, irq is generated. and then, dctq_busy signal go to low. cpu can read the state of dctq by referencing dctq_busy. in this document, for convenience, dctq operation means dct, quantisation, dequantisation and, inverse dct operations. hclk dctq_start dctq_busy irq dct/q/iq/idct operating period by opunit mb state figure 25-2. dctq operation timing diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -3 separated clock domain dctq ip has two clock domains. the one is a system bus clock domain. and, the other is a dctq core clock domain. these two clock domains are independent. however, it is recommended to use integer number division for dctq core clock. for low power consumption, if possible, lower dctq core clock is requested within codec performance. system bus clock dctq core clock dct/q iq/idct divide counter 1/1 ~ 1/30 pll divide counter figure 25-3. dctq clock domain dct a separable 2-dimensional discrete cosine transform (dct) is used. fuv n cucv f xy xu n yv n y n x n (,) () () (,)cos () cos () = ++ = ? = ? cu cv (), () = for u,v = 0 = 1 otherwise in this ip, n value is fixed to 8. before quantisation, f(u,v) is rounded. for reducing multiplication and reducing hardware size, row-column decomposition and chen?s algorithm is used. idct inverse dct module follows next equation. fxy n cucvfuv xu n yv n v n u n (,) () () (,)cos () cos () = ++ = ? = ?
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25-4 quantisation the quantisation parameter qp takes integer values from 1 to 31. the quantisation stepsize is 2xqp. cof a transform coefficient to be quantized. level absolute value of the quantized version of the transform coefficient. cof? reconstructed transform coefficient. intra dc (in mpeg-4 mode) level = cof // dc_scaler others for intra: level = |cof| / (2xqp) for inter: level = (|cof| - qp/2) / (2xqp) clipping to [-127:127] is performed for all coefficients except intra dc. the sign of cof is then added to obtain cof? : cof? = sign(cof) x |cof| dequantisation intra dc (in mpeg-4 mode) cof? = level x dc_scaler others |cof?| = 0, if level = 0 |cof?| = 2 x qp x level + qp, if level 0, qp is odd |cof?| = 2 x qp x level + qp ? 1, if level 0, qp is even clipping is [-2048:2047] is performed before idct.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -5 frame memory map the frame memories for dctq are shown in figure 1-4. t he padding area of reference frame fixed to 16 pixel extensions from original image to outsides in any other image sizes. because of dctqed bits per pixel, the dctqed frame memory size is double compared to original fr ame size. show the bit format in figure 1-6. q- information frame consists of the words of q-information by macroblock units. qcif y 176 144 reference frame memory size 208 176 start address location of register padding area qcif cb 88 72 104 88 qcif cr 88 72 104 88 qcif y 176 144 qcif cb 88 72 qcif cr 88 72 current frame memory size start address location of register current frame memory size = (176x144) + (88x72) + (88x72) = 38016 bytes reference frame memory size = (208x176) + (104x88) + (104x88) = 54912 bytes dctqed frame memory size = (352x144) + (176x72) + (176x72) = 76032 bytes q-inform memory size = 4 x 99 = 396 bytes qcif y 352 144 qcif cb 176 72 dctqed frame memory size start address location of register qcif cr 176 72 q- inform word 99 q-information frame memory size start address location of register figure 25-4. dctq frame memory map in qcif case
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25-6 q-information after dctq register setting, the first step of operations is the read of q-information for macroblock. the dctq engine observes the q-information and then determines the intra- or inter-modes, mb skip mode and, pick up quantisation information. for cbp mode in the decoder, software has to write zero coefficients into the each skipped 8x8 blocks. in mb-skip case that is not_coded( inter, zero-mv), in the decoder, dctq operation can be skipped for next mb operation. this mb-skip mode is not recommended with vlc in the encoder. reserved intra/ inter qp step mb skip inform 0 5 6 10 11 12 31 msb lsb 1 = intra mb 0 = inter mb 31 quantization step size (1 ~ 31) 6'b111111 = mb skip 6'b000000 = normal figure 25-5. q-information structure
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -7 bit format the dma operations are performed with word units. internal memory accesses are mainly byte based. the dctq operations use the 9, 12 bits. only little endian is supported in the words. curlm mcdlm - dct q iq idct + reclm dctq lm q-info word word word word 8-bit 8-bit 8-bit 9-bit 12-bit 12-bit 12-bit 12-bit 5-bit 9-bit 8-bit s 16-bits s 11-bit 12-bits 32-bits s 16-bits s 11-bit 12-bits 1) word 32-bits 8-bit 8-bit 8-bit 8-bit 32-bits 8-bit 8-bit 8-bit 8-bit 32-bits 8-bit 8-bit 8-bit 8-bit curlm : current mb local sram, mcdlm : mced mb local sram, dctqlm: dctqed mb local sram, reclm : reconstructed mb local sram 1) view the q-inform structure in figure 1-5. figure 25-6. dctq bit-format output bit-format of coefficient is incompatible with 2?s compliment for software. for getting sign, check the msb of output coefficient. and, lower 12-bits are levels for vlc. for block skip mode in decoder, software can put the ?0? coefficients into coefficient memory. in inter-mode, this zero residuals add by mced pixels for reconstruction image.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25-8 transposed coefficeint output the coefficient outputs of dctq are transposed in 8x8 block. one coefficient is stored into the half word. in memory, the sequences of coefficient are 0 -8-16-24- etc. in macroblock level, the output sequence of 6 blocks are as shown in below diagram. 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 y blocks c blocks transposed block 0 8 16 24 32 40 48 56 0 31 16 15 . . . 1 9 17 25 33 41 49 57 . . . . . . 32-bit sdram memory map 0x20000000 0x20000004 0x20000008 0x2000000c address offset (1 line) 0x20000058 0x2000005c 0x20000060 0x20000064 figure 25-7. transposed coefficient output for mb
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -9 software interface this mpeg-4 dctq provides a generic data-exchange method. it is recommended that the control register should be set at the last sfr setting sequence. mpeg-4 dctq special registers current frame y start address register register address r/w description reset value saycf 0x4900_0000 rw current frame luminance start address 0x00000000 saycf bit description initial state saycf [31:0] these bits indicate the luminance start address of current frame. 0x00000000 current frame cb start address register register address r/w description reset value sacbcf 0x4900_0004 rw current frame cb start address 0x00000000 sacbcf bit description initial state sacbcf [31:0] these bits indicate the chrominance cb start address of current frame. 0x00000000 current frame cr start address register register address r/w description reset value sacrcf 0x4900_0008 rw current frame cr start address 0x00000000 sacrcf bit description initial state sacrcf [31:0] these bits indicate the chrominance cr start address of current frame. 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25-10 reference frame y start address register register address r/w description reset value sayrf 0x4900_000c rw reference frame luminance start address 0x00000000 sayrf bit description initial state sayrf [31:0] these bits indicate the luminance start address of reference frame. 0x00000000 reference frame cb start address register register address r/w description reset value sacbrf 0x4900_0010 rw reference frame cb start address 0x00000000 sacbrf bit description initial state sacbrf [31:0] these bits indicate the chrominance cb start address of reference frame. 0x00000000 reference frame cr start address register register address r/w description reset value sacrrf 0x4900_0014 rw referenc e frame cr start address 0x00000000 sacrrf bit description initial state sacrrf [31:0] these bits indicate the chrominance cr start address of reference frame. 0x00000000 dctqed frame y start address register register address r/w description reset value saydqf 0x4900_0018 rw dctqed fr ame luminance start address 0x00000000 saydqf bit description initial state saydqf [31:0] these bits indicate the luminance start address for storing dct and quantized outputs. 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -11 dctqed frame cb start address register register address r/w description reset value sacbdqf 0x4900_001c rw dctqed frame cb start address 0x00000000 sacbdqf bit description initial state sacbdqf [31:0] these bits indicate the chrominance cb start address for storing dct and quantized outputs. 0x00000000 dctqed frame cr start address register register address r/w description reset value sacrdq f 0x4900_0020 rw dctqed frame cr start address 0x00000000 sacrdqf bit description initial state sacrdqf [31:0] these bits indicate the chrominance cr start address for storing dct and quantized outputs. 0x00000000 quantisation factor start address register register address r/w description reset value saqp 0x4900_0024 rw qp start address 0x00000000 saqp bit description initial state saqp [31:0] these bits indicate the qp start address for quantisation informations. 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25-12 image size register register address r/w description reset value imgsize 0x4900_0028 rw image horizontal and vertical pixel number 0x00000000 because dctq engine operates by macroblock unit, the horizontal and vertical pixel numbers should be the multiple of 16. for example, you can extract the exact svga image size after 800x608 dctq operation with dummy pixels. imgsize bit description initial state image_x [28:16] image horizontal pixel number 0 image_y [12:0] image vertical pixel number 0 sh q register register address r/w description reset value shq 0x4900_002c rw short header quantization mode 0x00000000 shq bit description initial state is_shq [ 27 ] 0 : mpeg-4 dc_scaler q-mode for intra-dc 1 : short header q-mode (/8,*8) for intra-dc 0 reserved [ 26 :0] must be zero 0 reserved sfr 0x49000030 control register register address r/w description reset value dctqctrl 0x4900_0034 rw control register 0x00000000 dctqctrl bit description initial state reserved [31:30] reserved 0 coeff_not_write [29] coefficients write operation to memory can be skipped with vlc ip ?on? state. in this case, dctq engine write the coefficient to the internal memory of vlc directly. 0 with_vlc [28] dctq operates by mb-unit with watching vlc operation (busy). in decoder mode, this bit must be zero. if only dctq is operating, 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor mpeg-4 dctq 25 -13 this bit should be zero. dct_only [27] quantization skip for jpeg mode 0 idct_only [26] de-quantization skip for jpeg mode 0 swrst [25] this bit indicates the software reset of mpeg-4 dctq. 0 opunit [24:8] these bits controls the number of dctq operations by macroblock unit. if these bits are 14?d99 in qcif size, dctq operates during one frame without command. 0 dctqbsy [7] this bit indicates the busy state of dctq. 1 = dctq is operating. 0 = dctq is not operating. 0 dctqst [6] this bit indicates the start of dctq operation. this bit is auto- cleared. 0 reserved [5] reserved 0 ish263 [4] this bit indicates that the format of current dctq operation is h.263 or not. 1 = h.263 (without padding) 0 = mpeg-4 (with padding) 0 reserved [3] reserved 0 isenc [2] this bit indicates that the current dctq operation is encoding or not. 1 = encoding 0 = decoding 0 reserved [1] reserved 0 frst [0] this bit indicates the frame start signal, which is active only first opunit. 1 = frame start 0 = normal 0 reserved sfr 0x49000038 reserved sfr 0x4900003c notes ? it is needed for software-reset to convert from encoder to decoder or from decoder to encoder.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-1 vlx (preliminary) overview vlx module consist of vlc( variable length coding )and vld( variable length decoding ) module. vlc block does the entropy coding in mpeg4 system. it assigns small bits to a symbol that occurs frequently in the source data. on the other hand, it assigns large bits to a symbol that occurs rarely. as a result, the size of the coded data is smaller than that of the original. mpeg4 used a predefined table that assigns a code to each symbol (run, level, last ) and cannot be redefined by the user in mpeg4 simple profile. vlc received coefficient data and control signal from dctq h/w module. so sfr control bits must be set same value in dctq module sfr data in vlc mode. vld block does the entropy decoding in mpeg4 system. it reads the coded bit stream from the main memory, extracts one code from the coded bit stream, and generates the symbol from the extracted code. as the length of a code is variable, vld block searches the coded bit stream step by step and compares the intermediate code value with the code table to get a complete code value. vld module is only 1 macro block operation so that always need to control interface between cpu. s/w must to be known the time of end of mb, so polling or interrupt signal generation in vld h/w. vlc and vld operation are not supported operation simultaneous. if intra macro block in vld mode need to dc prediction decoding and inverse scanning to use in dctq h/w module. and inter block in vld mode don?t need extra operation to use dctq module. vlx module designed for amba2.0 and has two dedicated dma, and 1 master and 1 slave ahb interface. feature - mpeg-4 simple profile - amba ahb interface - use dedicated dma - programmable image size qcif, cif, vga, qvga etc. - include dc prediction in vlc mode.. - interrupt and polling mode supported - support mpeg4 simple profile basic table excluding reversible vlc table
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-2 mpeg-4 vlx( variable length coding, decoding ) operation coeff mem. vlx dctq vlx ctrl. ahb external mem. i/f coeff i/f ctrl. i/f ahb i/f ahb master i/f ahb slave i/f vlc path vld path figure 26-1 vlx top interface block diagram vlc vlc block has 3 major blocks to code the input symbol s. they are vlc coder, run-length coding (rlc), dc prediction blcok. run-length coder(rlc). the output of the zigzag address generator is the sequence of the dct coefficients that read in zigzag order or dctq zigzag order . these coefficients are coded to rl c. rlc coder result is last, run, level value. in mpeg4 mode, the ac coefficients are coded to 3- d rlc code: (last, run,level). run is the zero number before the non-zero value, level. the last indicates that the level is the last non-zero value in the dct block. rlc coder searched the 8x8 blocks of transform coefficients are scanned with ?zigzag? scanning. zigzag order is explained figure. 26-2
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-3 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 64 figure 26-2 zigzag scanning method a three dimensional variable length coder is used to code transfo rm coefficients. an event is a combination of three parameters last 0 : there are more nonzero coefficients in the block. 1 : this is the last nonzero coefficient in the block. run number of zero coefficients preceding the current nonzero coefficient. level magnitude of the coefficient. the most commonly occurring combinations of last, run, level are coded with variable length codes given standard table. the remaining combinations, no matc hed case in table use three escape mode coding. first, level vaule change level minus lmax( lmax is defined by run . second, run value change run minus rmax ( rmax is defined by level ). last, flc, fixed length coding, are coded with a 22 bit word fixed length coding consisting of escape( 7 bit ), last(1 bi t ), run( 6 bit ),level(8 bit), coding used. entropy coder entropy coding is performed after the run-length coding. mpeg4 in simple profile uses a predefined table that gives the code and the length of the code for each symbol. entropy coder use many predefined table, dc table, intra luminance table, intra chrominance table, various e scape table. etc.. . so, the table in mpeg4 can be fixed in hardware to speed up the entropy coding using dire ct matching method. it supports only the mpeg4 simple profile, the table is hardwired to speed up the vlc and to lower the power consumption. dc prediction coder vlc support dc prediction operation. but ac prediction is not supported vlx module. so scanning method is always zigzag scanning. dc prediction value calculat es below fomular. assume, ?x?, ?a?, ?b? and ?c? correspondingly refer to the current block, the previ ous block, the block above and to the left, and the block immediately above as shown.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-4 a b c d x macroblock y or or figure 26-3 previous neighboring blocks used in dc prediction the differential dc is then obtained by subtracting the dc prediction, dcx? from dc of block ?x?. if (|dca - dcb| < |dcb - dcc|) dcx? = dcc else dcx? = dca dcx = dcx ? dcx? dc prediction h/w support q-step scaling method. q-step scaling method is to compensate for differences in the quantisation of previous horiz ontaly adjacent or vertically adjacent blocks used in ac prediction of the current block, scaling of prediction coefficients becomes necessary. thus the prediction is modified so that the predictor is scaled by the ratio of the current quantisation stepsize and the quantisation stepsize of the predictor block. vlc mode operations sequence. - receiving the data and control signal from the dctq h/w module. - 1 macro block data, zigzag ordered data receive form dctq module and data save coef_mem in the vlx h/w module . - sfr control bits already must be set. - the value, after run-length coding, is coded with intra, inter, escape run, escape level , dc code table, and then saved external memory. - vlc output save external memory on 1 word value. no t coded information, from msb to lsb data. {word count(16bit), bit count(16bit) }, vlc coeff. ordered save.vlx output in vlc mode are cbp information, word count, bit count vlced stream data. figure 26-4 show the output format in vlc mode. - cbp information : coded block pattern explain mb data exist or not . if coded block patter value 1 , that component has no dctq coefficient data. - one mb has six block so cbp information is six bit output. 0 bit is y0 block and 5 bit is cr block. figure 26-4 show the cbp bit information.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-5 external memory cbp word count bit count vlc stream vlced addr . . . . . . cbp word count bit count vlc stream . . . 128word( offset ) first mb data second mb data vlced addr + (128*4) word count bit count . . . cbp value cr cb y3 y2 y1 y0 1mb = 6 block big-endian value figure 26-4 vlc output bit stream format - output of encoder, saved data in memory, is big-endian data - interrupt signal or busy signal generated by end of op_unit processing. interrupt signal generation can be controlled by int_enable bit. - busy signal put to dctq module and be set sfr bit. hclk w rite_start ( from dctq ) vlx_busy vlx_irq vlxoperating period by one mb state dctq coeff. writting period figure 26-5 vlc start, busy, and interrupt signal timing diagram. at the vop layer, intra_dc_vlc_thr allows switching between dc intra vlc and ac intra vlc when coding dc coefficients of intra macroblocks. when the intra ac-vlc is turned on, intra-dc transform coefficients are not handled separately any more, but treated the same as all ac coefficients. that means a zero intra-dc will not be coded but will si mply increase the run for the following ac-coefficients. but this h/w set intra_dc_thr value fixed zero value, so always threated dc coefficients.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-6 vld vld h/w support only coefficient bit stream variable length decoding. except header decoding, intra dc/ac inverse prediction. so vld h/w need to communicate to s/w per macro block. this operation show figure 26- 6 . bit_saddr 0 31 16 start_bit_cnt 031 bit stream vlc_eaddr end_bit_cnt 031 big-endian data figure 26-6 vld bit stream h/w and s/w interface format. s/w must be set bit_saddr and start_bit_cnt and bitstream data. bit_saddr is address of start coefficient bit stream. and start_bit_cnt is start bit of current macro block bit stream. and bitstream data must be big-endian data . vld h/w generate vlc_eaddr and end_bit_cnt value after macro block vld operation. before next macro block start s/ w have to find bit_saddr and start_bit_cnt after header parsing and vld. decoded coefficient data saved external memory y image, cb image, and cr image. figure 26-7 is example external memory amount. so special function register y_start_addr, cb_start_addr, cr_start_addr must be set. vlded frame memory size = (352x144) + (176x72) + (176x72) = 76032 bytes qcif y 352 144 qcif cb 176 72 vlx frame memory size start address location of register qcif cr 176 72 figure 26-.7 external memory amount in vld mode.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-7 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 32bit 1 mb luminance 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 1 frame image 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 1 6 2 7 16 15 28 29 3 4 10 5 8 14 17 27 30 43 9 12 13 18 26 31 42 44 19 25 32 41 45 54 11 24 20 33 46 40 53 55 21 22 36 23 34 39 47 52 56 61 35 37 38 48 51 57 60 62 49 50 58 59 63 0 figure 26-8 vld output coefficient format vld block has 3 major blocks. they are shifter, ent ropy decoding, run length decoding (rld), shifter include entropy coder. the operation and the sequence of the vld operation are reverse to the vlc . shifter the shifter gives the coded bit stream to the entropy-decoding block and does the shifting operation requested from the entropy-decoding block. the sh ifting operation is executed during the decoding process to give the left aligned coded bit stream to the entropy-decoding block. entropy decoder the entropy-decoding process has two steps. in first step, it extracts one code from the coded bit stream from the shifter and in second, it finds the symbol address corresponding to that code. in general case, during the process to extract one code the address for the symbol is calculated. the output of entropy decoder are run, level, last value. these value is input of rld module.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-8 run length decoder the output of the entropy decoding is (last,run, l evel) in mpeg mode. they are decoded to a sequence of the coefficients. this operation is done in the run-length decoding block. it is the reverse operation of the rlc block. and reads the sequence of coefficients from the run-length decoding block and writes the coefficients to the dct/q memory in zigzag address order or dctq zigzag addre ss order . this is the reverse operation in vlc rlc. vld operation . - vld is operated by 1 mb opunit. - decoding start address and bit count are accepted on each mb by s/w processing. 31 0 (sfr : bit_count ) 8 16 24 31 figure 26-9 msb is first bit value in output bit stream - vld output is saved image format in external memory. figure 26-7, 26-8 show the external memory - dc prediction inverse coding and scanning are need in s/w processing in intra mode. - vld processing explained figure 26-10 vld flow c hart. vld flow chart is partitioned s/w processing and h/w processing.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-9 vop header dec. get vop information mb header dec. mb mode information mb == op_unit no yes on vld sfr set and triggering. cbp information bit_saddr, start_bit_cnt coefficient vld operation polling sigal or interrupt signal gen. get vld_eaddr end_bit_cnt intra yes intra dc/ac inverse prediction and scannig yes dctq transter no mb == frame on yes no h/w operation s/w operation figure 26-10 vld flow chart and s/w and h/w processing partition. - start signal and busy signal and interrupt relation is fig.26-11 hclk vlx_cpu_start or w rite_start ( from dctq ) vlx_busy vlx_irq vlxoperating period by opunit mb state figure 26-11 start signal, busy signal and interrupt signal in vld mode.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-10 vlx( vlc and vld ) special registers vlx common sfr . register address r/w description reset value common1 0x4 9 40_0000 r/w vlx common control register 1 0x0000_0000 common1 bit description initial state vlx on [0] vlx system on / off control bit, not start bit 0x0 - [1] reserved 0x0 frame_start [2] 1 : frame start 0 : not frame start 0x0 vlx_start [3] 1 : encoder or decoder start 0 : disable 0x0 enc_mode [4] 1 : encoder 0 : decoder 0x0 int_enable [5] 1 : interrupt mode enable 0 : disable 0x0 - [8:6] reserved 0x0 op_unit_sfr [20:9] operation mb count 0x000 - [21] reserved 0x0 note 1. vlx _on bit is on / off control. 2. frame start and cpu start must down before next co mmon1 set. because of these signal is generated one pulse signal in vlx internal module ( only detect rising edge this signal ). 3. frame_start signal must be set 1 time per 1 frame. a nd it must be set 0 before next op_unit processing start. 4. enc_mode 1 : vlc operation , 0 : vld operation. 5. int_enable 0 : only polling mode ( busy signal is vlx_busy value in vlx_out1 special function register .) 6. op_unit sfr count value of macro block operation in vlc mode. interrupt signal generation on end of op_unit. op_unit_sfr must be set 1 value in vld mode. 7. common[1] and common[8:6] must be set value ?0? 8. common[21] must be set value ?1?. frame start addr register address r/w description reset value frame_start_y 0x4 9 40_0004 r/w y coeff. frame start address 0x0000_0000 frame_start_y bit description initial state
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-11 y img frame start addr [31:0] y coeff. frame start address in vld mode 0x0000_0000 register address r/w description reset value frame_start_cb 0x4940_0008 r/w cb c oeff. frame start address 0x0000_0000 frame_start_cb bit description initial state cb img frame start addr [31:0] cb coeff. frame start address in vld mode 0x0000_0000 register address r/w description reset value frame_start_cr 0x4940_000c r/w cr c oeff. frame start address 0x0000_0000 frame_start_cr bit description initial state cr img frame start addr [31:0] cr coeff. frame start address in vld mode 0x0000_0000 vlx control register( vlx_con) register address r/w description reset value vlc_con1 0x4940_0010 r/w control register in vlc mode 0x0000_0000 vlc_con1 bit description initial state img_xsize_sfr [9:0] image x size set register 0x000 - [10] reserved 0x0 sel_scan_sfr [12:11] scanning method select control bits. 0x0 - [13] reserved 0x0 sw_reset [14] s/w reset active high. 0x0 note 1.img_xsize_sfr is pixel count value. ex ) qcif = 176, cif = 352 2. 2?b00 : zigzag scan, 2?b11 : dctq zigzag format by dctq module format , others : ordered format. 3. s/w reset active high. and need to be down after high. 4. common[10] must be set value ?1? 5. common[13] must be set value ?0?
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-12 register address r/w description reset value vlc_con2 0x4940_0014 r/w reserved - register address r/w description reset value vlc_con3 0x4940_0018 r/w vlc bit stream start addr. 0x0000_0000 vlc_con3 bit description initial state vlced_addr [31:0] external address saved vlced output stream. 0x0000_0000 note. vlced addr is bit stream base address output in vlc mode. vlced addr[8:0] bit must be set 0 value!!. register address r/w description reset value vlc_con4 0x4940_001c r/w reserved 0x0000_0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor vlx 26-13 vld control register( vld_con) register address r/w description reset value vld_con1 0x4940_0020 r/w vld control value setting register 0x0000_0000 vld_con1 bit description initial state - [11:0] reserved - start_bit_cnt [17:12] first bit count value when vld start 0x00 is_intra_vld [18] 1 : intra, 0 : inter mode in vld 0x0 - [19] reserved - cbp_vld_sfr [25:20] cbp value 0x00 qp_sfr [30:26] qp value 0x00 - [31] reserved - note 1. bit_stuff_sfr is bit count number of first start macro block bit streams. 2. bit[11:0], bit[19] must be set value ?0?. 3. bit[31] must be set ?0x1? register address r/w description reset value vld_con2 0x4940_0024 r/w vld bit_saddr 0x0000_0000 vld_con2 bit description initial state bit_saddr [31:0] vld bit stream start bit in vld mode. 0x0000_0000 register address r/w description reset value vld_con3 0x4940_0028 r/w reserved -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. vlx S3C24A0 risc microprocessor 26-14 vlx output register 1 ( vlx_con 1 ) ? read only register address r/w description reset value vlx_out1 0x4940_002c r vlx output information register. 1 0x0000_0000 vlx_con1 bit description initial state vld_busy [0] vlx busy signal 0x0 n_st_bit_cnt [6:1] next start bit count 0x00 vlx output register 2 ( vlx_con 2 ) ? read only register address r/w description reset value vlx_out2 0x4940_0030 r vlx output information register. 2 0x0000_0000 vlx_con2 bit description initial state n_start_addr [31:0] next start address. 0x0000_0000 note 1. n_start_bit_cnt is next start bit counter number for next mb decoding.. 2. n_start_addr is next start address for next mb decoding.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-1 post processor (preliminary) 1. overview post processor performs video/graphic scale, video fo rmat conversion and color space conversion. it is composed of data-path, dma controller and register files as shown in the overall block diagram of figure 27-1. overall features are summarized as follows. figure 27-1. block diagram of post processor overall features amba ahb v2.0 compatible interface dedicated dma with offset address 3 channel scaling pipelines for video/gr aphic scaling up/down or zooming in/out video input format: 420, 422 format graphic input format: 16-bit (565format) or 24-bit register files dma controller scale & format conversion csc pre scale main scale pre scale main scale pre scale main scale color space con. y cb cr a hb bus rgb line memory infifo outfifo line memory line memory
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-2 output format: 16-bit (565 format) / 24-bit graphic data programmable source and destination image size up to 2048 2048 resolution programmable scaling ratio format conversion for video signals color space conversion separate processing clock with ahb interface clock
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-3 2. a source and destination image data format various source and destination image formats can be selected according to the mode configuration as described in table 27-1. source image format is one of ycbcr420, ycbcr422, rgb16-bit (565format) and rgb 24-bit format. destination image format is either rgb 16-bit (565format) or rgb 24-bit. in the case of ycbcr420 source image format, eac h component of y, cb and cr is stored in each own separated address space without any in terleaving as shown in case a of figure 27-2 (a) and figure 27-3. in the other cases, either byte or half-word interleaving is applied within unified address space as shown in figure 27-2 (b). byte interleaving order of ycbcr422 source image is selectable either ycbycr or cbycry as shown in case b and c of figure 27-2 (b) and figure 27-3. byte order of rgb 24-bit and half-word order of rgb 16-bit are shown in case d and e of figure 27-2 (b) and figure 27-3. in both cases of ycbcr420 and ycbcr422 source im age format, whether mpeg4 format or mpeg2/h.263 format needs to be selected according to the sampling position of the chroma information as shown in figure 27-4. all source and destination image data need to be stored in memory system aligned with word boundary. it means that neither byte nor half-wo rd size dma operations are supported (see chapter 27-4 for dma operation). therefore, the width of source and destination image should be selected to satisfy the word boundary condition (see chapter 27-3 for image size). table 27-1. mode confi guration for video/graphic source fo rmat and the corresponding data format description mode[8] src420 mode[3] inrgb mode[2] inter- leave mode[1] inrgb format mode[0] inycbcr format video/graphic format data format in fig27-2 and 3 1001 420 ycbcr format a 0 0 1 1 0 422 ycbycr format b 0 0 1 1 1 422 cbycry format c 0111 rgb 24-bit true color d 0110 rgb 16-bit format e
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-4 word word msb lsb msb lsb b c a d e memory space memory space (a) non-interleaving (b) interleaving figure 27-2 data format stored in external memory 31 24 23 16 15 8 7 0 case a y/cb/cr n+3 y/cb/cr n+2 y/cb/cr n+1 y/cb/cr n case b y n+1 cb n y n cr n case c cb n y n+1 cr n y n case d don?t care r n g n b n 31 27 26 21 20 16 15 11 10 5 4 0 case e r[4:0] g[5:0] b[4:0] r[4:0] g[5:0] b[4:0] pixel n+1 pixel n figure 27-3 byte and half-word organization y cb cr 1 frame video data or graphic data 1 frame y y y y cb cb cb cb cr cr cr cr ycb y cr cb y cr y pixel n+1 pixel n x r g b
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-5 (a) ycbcr420 (mpeg2/h.263) (b) ycbcr420 (mpeg4) (c) ycbcr422 (mpeg2/h.263) (d) ycbcr422 (mpeg4) figure 27-4 sampling position of ycbcr420 and ycbcr422 format (: luma sample and : chroma sample) dx dy 1/2dx 1/2dx 1/4dy 1/2dy 1/2dy dx dy 1/4dx 1/2dx 1/2dx 1/4dy 1/2dy 1/2dy dx dy 1/2dx 1/2dx 1/4dy 1/2dy 1/2dy dx dy 1/4dx 1/2dx 1/2dx 1/4dy 1/2dy 1/2dy
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-6 3. image size and scale ratio the rgb graphic source image size is determined by number of pixels along to horizontal and vertical directions. ycbcr420 and ycbcr422 source image size is determined only by numbers of y samples along to horizontal and vertical direct ions. destination image size is determin ed by dimension of final rgb graphic image, after color space conversion if source image is ycbcr image. as explained in the previous sect ion, src_width and dst_width satisf y the word boundary constraints such that the number of horizontal pixel can be represented to kn where n = 1,2,3, ? and k = 1 / 2 / 8 for 24bpprgb / 16bpprgb / ycbcr420 image, respectively. figure 27-5 source destination image size the other control registers of pre-sc aled image size, pre-scale ratio, pre-sc ale shift ratio and main scale ratio are defined according to the following equations. if ( src_width >= 64 dst_width ) { exit(-1); /* out of horizontal scale range */ } else if (src_width >= 32 dst_width) { prescale_h_ratio = 32; h_shift = 5; } else if (src_width >= 16 dst_width) { prescale_h_ratio = 16; h_shift = 4; } else if (src_width >= 8 dst_width) { pr escale_h_ratio = 8; h_shift = 3; } else if (src_width >= 4 dst_width) { pr escale_h_ratio = 4; h_shift = 2; } else if (src_width >= 2 dst_width) { pr escale_h_ratio = 2; h_shift = 1; } else { prescale_h_ratio = 1; h_shift = 0; } prescale_dstwidth = src_width / prescale_h_ratio; dx = ( src_width << 8 ) / ( dst_width << h_shift); source image destination image src_width src_height dst_width dst_height
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-7 if ( src_height >= 64 dst_height ) { exit (-1); /* out of vertical scale range */ } else if (src_height >= 32 dst_height) { pr escale_v_ratio = 32; v_shift = 5; } else if (src_height >= 16 dst_height) { pr escale_v_ratio = 16; v_shift = 4; } else if (src_height >= 8 dst_height) { prescale_v_ratio = 8; v_shift = 3; } else if (src_height >= 4 dst_height) { pr escale_v_ratio = 4; v_shift = 2; } else if (src_height >= 2 dst_height) { pr escale_v_ratio = 2; v_shift = 1; } else { prescale_v_ratio = 1; v_shift = 0; } prescale_dstheight = src_he ight / prescale_v_ratio; dy = ( src_height << 8 ) / ( dst_height << v_shift); prescale_shfactor = 10 ? ( h_shit + v_shift);
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-8 4. dma operation of source and destination image there are three address categories such as start addr ess, end address and offset address for dma operation. each address category consists of three source addr ess components of y/cb/cr and one destination address component of rgb. if a source image is stored by t he non-interleaved format such as ycbcr420, all source address components are valid as shown in figure 27-6 (a ). if a source image is stored by the interleaved format such as a rgb graphic format or an ycbcr422 forma t, only y component of three source components is valid and two chroma address components are invalid as show n in figure 27-6 (b). the details of start and end address are define as follows. (a) non-interleaving (b) interleaving figure 27-6 start and end address set a ccording to memory allocation type y cb cr video data or graphic data source image destination image addrstart_y addrend_y addrstart_cb addrend_cb addrstart_cr addrend_cr addrstart_rgb addrend_rgb addrstart_y addrend_y addrstart_rgb addrend_rgb rgb rgb
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-9 start address start address of addrstart_y/cb/cr/rgb points t he first word address where the corresponding component of y/cb/cr/rgb is read or writt en. each one should be aligned with word boundary (i.e. addrstart_x[1:0] = 00). addrstart_cb and addrstart_cr are valid only for the ycbcr420 source image format. end address addrend_y = addrstart_y + memory size for the component of y = addrstart_y + (src_width src_height) byte size_per_pixel + offset_y (src_height-1) addrend_cb (valid for ycbcr420 source format) = addrstart_cb + memory size for the component of cb = addrstart_cb + (src_width/2 src_height/2) byte size_per_pixel + offset_cb (src_height/2-1) addrend_ cr (valid for ycbcr420 source format) = addrstart_ cr + memory size for the component of cr = addrstart_cr + (src_width/2 src_height/2) byte size_per_pixel + offset_cr (src_height/2-1) addrend_rgb = addrstart_rgb + memory size for the component of rgb data = addrstart_rgb + (dst_width dst_height) bytesize_per_pixel + offset_rgb (dst_height-1) where, offset_y/cb/cr/rgb = memory size for offset per a horizontal line = number of pixel (or sample) in horizont al offset bytesize_per_pixel (or sample) bytesize_per_pixel = 1 for ycbcr420 2 for 16-bit rgb and ycbcr422 4 for 24-bit rgb
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-10 offset is used for the following two s ituations. one is to fetch some parts of source image in order to zoom in/out as shown in figure 27-7 (a). the other is to restore destinat ion image for pip (picture-in-picture) applications as shown in figure 27-7 (b). of course, the word boundary constraints should be satisfied in both cases. original image source image src_width src_height offset destination image (zoom in/out) dst_width dst_height a) zoom in/out source image src_width src_height background image b) pip destination image(pip) dst_width dst_height offset figure 27-7 offset for (a) source image for zoom in/out operation and (b) destination image for pip applications 5. starting and terminating of post processor starting and terminating the operation of post-processor are controlled by two control register such as postenvid and postint as shown in figure 27- 8. ?postenvid? triggers the operation of post processor. it is automatically de-asserted when all ope rations of the given frame are completed. before asserting ?postenvid?, all control registers should be set to the proper value as explained in the previous chapters. when all operations are comp leted, interrupt pending register is asserted (postint=1), if interrupt enable signal is asserted (inten=1). the postint signal, directing to the interrupt controller, should be cleared by the interrupt service routine. otherwise, polling postenvid is used to detec t the end of the operation.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-11 figure 27-8 start and termination of the operation of post processor 6. register file lists mode control register register address r/w description reset value mode 0x4a100000 r/w mode register [9:0] 0xb12 mode bit description initial state reserved 11 this bit should be ?1?. 1 reserved 10 this bit should be ?0?. 0 mpeg4 [9] sampling position of chroma info rmation. 0 for h.263/mpeg2 and 1 for mpeg4. it is valid only for ycbcr source image (i.e. inrgb = 0) 1 src420 [8] 0 for ycbcr422 and 1 for ycbcr420 source format. it is valid only for ycbcr source image (i.e. inrgb = 0) 1 inten [7] interrupt enable. it determines whether the postint signal is asserted or not, when the processing of the current frame is finished. 0: disable, 1 : enable. 0 postint [6] interrupt pending bit. if inten is enabl ed, it is automatically asserted right after finishing operation of the current frame. it should be cleared by interrupt service r outine. 0 : disable, 1 : enable. 0 postenvid [5] enable video processing. it turns on the operation of postprocessor. it is de-asserted automatically afte r operation of the current frame is finished. it should be disabled (postenvid=0) during control 0 users set (start operation) automatic clear/assertion (terminate operation) user clear if asserted postenvid postint (inten=1) (inten=0) control register set
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-12 register configuration state. outrgbformat [4] it determines the output format of destination image. 0 for 16-bit (565 format) rgb and 1 for 24-bit rgb. 1 inrgb [3] it indicates the input color space of source image. 0 for ycbcr or 1 for rgb. 0 interleave [2] it indicates the data format of ycbcr. 0 for non-interleaved format (each component of y, cb and cr is access by the word). 1 for interleaved format (all components of y, cb and cr are mixed inside single word). it should be 1 when source image is rgb data (or inrgb =1). 0 inrgbformat [1] if the source image is in rgb color space (or inrgb=1), it indicates the data format of graphic image. 0 for 16-bit (565 format) and 1 for 24-bit. otherwise (or inrgb=0), it should be remains to 1. 1 inycbcrformat [0] it determines the byte organization of word data when the source image is interleaved ycbcr form at (inrgb=0 and interleave=1). 0 for ycbycr(type b in fig. 27-2(b)) and 1 for cbycry (type c in fig.27-2(b) . 0 pre-scale ratio register register address r/w description reset value prescale_ratio 0x4a100004 r/w pre-scale ratio for vertical and horizontal. 0x0 prescale_ratio bit description initial state prescale_v_ratio [13:7] pre-scale ratio along to vertical direction (see chapter 27-3) 0x0 prescale_h_ratio [6:0] pre-scale ratio along to horizont al direction (see chapter 27-3) 0x0 pre-scale image size register register address r/w description reset value prescaleimgsize 0x4a100008 r/w pre-scaled image size 0x0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-13 prescaleimgsize bit description initial state prescale_dstheight [23:12] pre-scaled image height (see chapter 27-3) 0x0 prescale_dstwidth [11:0] pre-scaled image width (see chapter 27-3) 0x0 source image size register register address r/w description reset value srcimgsize 0x4a10000c r/w source image size 0x0 srcimgsize bit description initial state srcheight [23:12] source image height (see chapter 27-3) 0x0 srcwidth [11:0] source image width (see chapter 27-3) 0x0 horizontal main scale ratio register register address r/w description reset value mainscale_h_ratio 0x4a100010 r/w main scale ratio along to horizontal direction 0x0 mainscale_h_ratio bit description initial state mainscale_h_ratio [8:0] main scale ratio along to horizont al direction (see chapter 27-3) 0x0 vertical main scale ratio register register address r/w description reset value mainscale_v_ratio 0x4a100014 r/w main scale ratio along to vertical direction 0x0 mainscale_v_ratio bit description initial state
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-14 mainscale_v_ratio [8:0] main scale ratio along to vertic al direction (see chapter 27-3) 0x0 destination image size register register address r/w description reset value dstimgsize 0x4a100018 r/w d estination image size 0x0 srcimgsize bit description initial state dstheight [23:12] destination image height (see chapter 27-3) 0x0 dstwidth [11:0] destination image widt h (see chapter 27-3) 0x0 pre-scale shift factor register register address r/w description reset value prescale_shfactor 0x4a10001c r /w pre-scale shift factor 0x0 src_width bit description initial state prescale_shfactor [3:0] pre-scale shift factor (see chapter 27-3) 0x0 dma start address register register address r/w bit description reset value addrstart_y 0x4a100020 r/w [30:0] dma start address for y or rgb component of source image 0x2000_0000 register address r/w bit description reset value addrstart_cb 0x4a100024 r/w [30:0] dma start address for cb component of source image 0x2000_0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor post processor 27-15 register address r/w bit description reset value addrstart_cr 0x4a100028 r/w [30:0] dma start address for cr component of source image 0x2000_0000 register address r/w bit description reset value addrstart_rgb 0x4a10002c r/w [30:0] dma start address for rgb component of destination image 0x2000_0000 dma end address register register address r/w bit description reset value addrend_y 0x4a100030 r/w [30:0] dma end address for y or rgb component of source image (see chapter 27-4) 0x2000_62fc register address r/w bit description reset value addrend_cb 0x4a100034 r/w [30:0] dma end address for cb component of source image (see chapter 27-4) 0x2000_62fc register address r/w bit description reset value addrend_cr 0x4a100038 r/w [30:0] dma end address for cr component of source image (see chapter 27-4) 0x2000_62fc register address r/w bit description reset value addrend_rgb 0x4a10003c r/w [30:0] dma end address for rgb component of destination imag e (see chapter 27- 4) 0x2000_62fc offset register register address r/w bit description reset value
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. post processor S3C24A0 risc microprocessor 27-16 offset_y 0x4a100040 r/w [23:0] offset of y component for fetching source image (see chapter 27-4) 0 register address r/w bit description reset value offset_cb 0x4a100044 r/w [23:0] offset of cb component for fetching source image (see chapter 27-4) 0 register address r/w bit description reset value offset_cr 0x4a100048 r/w [23:0] offset of cr component for fetching source image (see chapter 27-4) 0 register address r/w bit description reset value offset_rgb 0x4a10004c r/w [23:0] offset of rgb component for restoring destination image (s ee chapter 27-4) 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-1 lcd controller (preliminary) overview the lcd controller within S3C24A0 consists of logic for transferring lcd image data from a video buffer located in system memory to an external lcd driver. the lcd controller supports 1-bit per pixel, 2-bit per pixel, 4-bit per pixel, 8-bit per pixel for interfacing with the palettized tft color lcd panel, 8-bit, 16-bit per pixel and 18-bit per pixel non-palettized color display. the lcd controller can be programmed to support the different requirements on the screen related to the number of horizontal and vertical pixels, data line width for the data interface, interface timing, and refresh rate. features video clock source hclk external panel interface supports up to 18 bit rgb i/f panel(rgb parallel mode) supports 6 bit rgb i/f panel(rgb serial mode) supports both rgb and bgr mode osd(overlay) supports 8 bpp (bit per pixel) palettized or non-palettized color displays for tft supports 16 and 18 bpp non-palettized color displays for color tft supports x,y indexed position supports 8 bit alpha blending : per plan or per pixel(18 bpp only) support 18 bit color key function color level of tft supports 1, 2, 4 and 8 bpp(bit per pixel) palettized color displays for tft supports 8, 16 and 18 bpp non-palettized color displays for tft display size supports 640x480, 320x240, 176x192 and others configurable burst length support programmable 4 / 8 / 16 burst dma operation dual palette 256 x 24 bit palette (2ea for each background and foreground image) soft scrolling horizontal : 1 byte resloution vertical : 1 pixel resolution virtual screen virtual image can has up to 16mb image size. double buffering frame buffer alternating by one control bit dithering patented 4x4 dither matrix implemetation
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-2 external interface signal name type source/destination description xvvclk output pad video clock signal xvhsync output pad horizontal sync. signal xvvsync output pad vertical sync. signal xvvden output pad video data enable/valid xvvd[17:12] output pad lcd pixel data output for red in rgb parallel mode lcd pixel data output in rgb serial mode xvvd[11:6] output pad lcd pixel data output for green in rgb parallel mode xvvd[5:0] output pad lcd pixel data output for blue in rgb parallel mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-3 block diagram regbank lcdcdma xvvclk xvhsync xvvsync xvvden timegen vidprcs xvvd[17:0] vidclkgen hclk figure 28-1. lcd controller block diagram the lcd controller within S3C24A0 is used to transfer the video data and to generate the necessary control signals such as , xvvsync, xvhsync, xvvclk, and xvvden . as well as the control signals, S3C24A0 has the data ports for video data, which are xvvd[17:0] as shown in figure 28-1. the lcd controller consists of a regbank, lcdcdma, vidprcs, timegen, and vidclkgen (see figure 28-1 lcd controller block diagram). the regbank has 26 programmable register sets and 256x24 palette memory which are used to configure the lcd controller. the lcdcdma is a dedicated dma, which it can transfer the video data in frame memory to lcd driver, automatically. by using this special dma, the video data can be displayed on the screen without cpu intervention. the vidprcs receives the video data from lcdcdma and sends the video data through the vd[17:0] data ports to the lcd driver after changing them into a suitable data format, for example 8- bit per pixel mode(8 bpp mode) or 16-bit per pixel mode(16 bpp mode). the timegen consists of programmable logic to support the variable requirement of interface timing and rates commonly found in different lcd drivers. the timegen block generates , xvvsync, xvhsync, xvvclk, and xvvden . the description of data flow is as follows: fifo memory is present in the lcdcdma. when fifo is empty or partially empty, lcdcdma requests data fetching from the frame memory based on the burst memory transfer mode(consecutive memory fetching of 4 / 8 / 16 words per one burst request without allowing the bus mastership to another bus master during the bus transfer). when this kind of transfer request is accepted by bus arbitrator in the memory controller, there will be 4 /8 /16 successive word data transfers from system memory to internal fifo. the total sizes of fifo are 128x2 words, which consist of 128 words for background fifo and 128 words foreground fifo, respectively. the S3C24A0 has two fifos because it needs to support the osd display mode. in case of one screen display mode, the background fifo could only be used. lcd controller supports overlay function which enables overlaying any image (osd, foreground image) which is small or same size can be blended with background im age with programmable alpha blending or color (chroma) key function.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-4 timing controller operation the timegen generates the control signals for lcd driver such as, , xvvsync, xvhsync, xvvclk, and xvvden signal. these control signals are highly related with the configuration on the lcdtcon1/2/3 registers in the regbank. base on these programmable configurations on the lcd control registers in regbank, the timegen can generate the programmable control signals suit able for the support of many different types of lcd drivers. the vsync signal is asserted to cause the lcd's line pointer to start over at the top of the display. the generation of vsync and hsync pulse is controlled by the configuration of both the hozval field and the lineval field in the lcdtcon3 register. the hozval and lineval can be determined by the size of the lcd panel according to the following equations: hozval = (horizontal display size) -1 lineval = (vertical display size) -1 divider 1/[(clkval+1)x2] hclk mux 0 1 vclk clkdir figure 28-2. clock selection the rate of vclk signal can be controlled by the clkval field in the lcdcon1 register. the table below defines the relationship of vclk and clkval. the minimum value of clkval is 0. xvvclk (hz) =hclk/ [(clkval+1) x2] the frame rate is vsync signal frequency. the frame rate is related with the field of vsync, vbpd, vfpd, lineval, hsync, hbpd, hfpd, hozval, clkval registers. most lcd driver needs their own adequate frame rate. the frame rate is calculated as follows; frame rate = 1/ [ { (vspw+1) + (vbpd+1) + (liineval + 1) + (vfpd+1) } x {(hspw+1) + (hbpd +1) + (hfpd+1) + (hozval + 1) } x { 2 x ( clkval+1 ) / ( frequency of clock source ) } ] table 28-1. relation between xvvclk and clkval (tft, freq. of video clock source=60mhz) clkval 60mhz/x xvvclk 1 60 mhz/4 15.0 mhz 2 60 mhz/6 10.0 mhz
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-5 :: : 63 60 mhz/128 492 khz
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-6 video operation the tft lcd controller within S3C24A0 supports 1, 2, 4 or 8 bpp(bit per pixel) palettized color displays and 8, 16 non-palettized high-color or 18 bpp non-palettized true-color displays. the tft lcd controller also supports on-screen display with 256-level alpha blending and color (chroma) key functions. the background image and foreground image (osd image) should have a frame buffer of each image. osd (on-screen display) : overlay osd (on screen display) and blending operation as shown in fig 28-3 are established for video overlay or other graphics applications. two blending schemes are provided according to the control bit of osd_bld_pix. one is per-pixel blending for 18 bpp mode display (osd_bld_pix = 1) and the other is per-plane bending for 8/16/18 bpp mode display (osd_bld_pix = 0). lcdb1addr1/2/3, lcdb2addr1/2/3 registers are defined to perform dma for osd image. four screen coordinates such as osd_left_top_x, osd_left_top_y, osd_right_bot_x and osd_right_bot_y determines where the osd image is located on the whole background image. the level of blending is controller by osd_alpha as following manner. new pixel = (1-alpha) background pixel + alpha foreground pixel where, alpha = 0 , if osd_alpha[7:0] = 0. alpha = i=1,2,,?7 osd_alpha[7-i]x2 -i o sd_alpha[7-i] , other. background frame buffer foreground frame buffer(osd) lcd controller system memory (osd_lefttop_x, osd_lefttop_y) (osd_rightbot_x, osd_rightbot_y) (a) memory allocation (b) blending fig 28-3 osd procedure
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-7 color-key function the S3C24A0 can support color-key function for the various effect of image mapping. color image, which is specified by color-key register , of osd layer will be substituted by background image for special functionality, as cursor image or pre-view image of the camera. background image foreground image blending color key fig 28-4 blending and color key function of osd
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-8 dual buffer the S3C24A0 lcd controller supports easy and fast way for the dual buffering of frame image. user can take two frame image buffer and select one fo r active frame buffer using the bdbcon (background double buffer control) and fdbcon (foreground double buffer control) register. pre-defined address sets of frame buffer 1 and frame buffer2 are described at frame buffe r register 1,2,3. so, user can select which buffer will be activated by setting of the bdbcon and fdbcon register. maybe, some applications should need simple changing method of frame buffer namely ?ping-pong display? . pre-view image of camera interface will be good example of dual buffering method. one frame should be used as a display buffer, and the other frame as a updating buffer by camera interface module.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-9 memory data format (tft) the lcd controller requests the specified memory format of frame buffer. the next table shows some examples of each display mode. 18 bpp display [bswp = 0, hwswp = 0] d[31:24] d[23:0] 000h alpha1 p1 004h alpha2 p2 008h alpha3 p3 ... note: d[31:24] are used to be the alpha value according to each pixel data when blending mode is per-pixel at 18 bpp. so, user must write appropriate value to this filed. p1 p2 p3 p4 p5 ...... lcd panel [memory storing order at 18 bpp] d[23:0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data r5 r4 r3 r2 r1 r0 x x g5 g4 g3 g2 g1 g0 x x b5 b4 b3 b2 b1 b0 x x x: don?t care, we recommend that those bits are filled with ?0?. [xvvd pin connection at 18 bpp/parallel mode] xvvd 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data r5 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b5 b4 b3 b2 b1 b0 [xvvd pin connection at 18 bpp/serial mode] xvvd 17 16 15 14 13 12 11 - 0 1 st data r5 r4 r3 r2 r1 r0 nc 2 nd data g5 g4 g3 g2 g1 g0 nc 3 rd data b5 b4 b3 b2 b1 b0 nc
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-10 16bpp display [bswp = 0, hwswp = 0] d[31:16] d[15:0] 000h p1 p2 004h p3 p4 008h p5 p6 ... [bswp = 0, hwswp = 1] d[31:16] d[15:0] 000h p2 p1 004h p4 p3 008h p6 p5 ... p1 p2 p3 p4 p5 ...... lcd panel [memory storing method at 16 bpp] (5:6:5) d[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 (5:5:5:i) d[15:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 data r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i [xvvd pin connection at 16 bpp/parallel mode] (5:6:5) xvvd17161514131211109876543210 data r4 r3 r2 r1 r0 n c g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 n c
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-11 (5:5:5:i) xvvd17161514131211109876543210 data r4 r3 r2 r1 r0 i g4 g3 g2 g1 g0 i b4 b3 b2 b1 b0 i [xvvd pin connection at 16 bpp/serial mode] (5:6:5) (5:5:5:i) xvvd 17 16 15 14 13 12 11 - 0 xvvd 17 16 15 14 13 12 11 - 0 1 st data r4 r3 r2 r1 r0 nc nc 1 st data r4 r3 r2 r1 r0 i nc 2 nd data g5 g4 g3 g2 g1 g0 nc 2 nd data g4 g3 g2 g1 g0 i nc 3 rd data b4 b3 b2 b1 b0 nc nc 3 rd data b4 b3 b2 b1 b0 i nc 8bpp display [bswp = 0, hwswp = 0] d[31:24] d[23:16] d[15:8] d[7:0] 000h p1p2p3p4 004h p5p6p7p8 008h p9 p10 p11 p12 ... [bswp = 1, hwswp = 0] d[31:24] d[23:16] d[15:8] d[7:0] 000h p4p3p2p1 004h p8p7p6p5 008h p12 p11 p10 p9 ... [memory storing method at non-palettized 8 bpp] d[7:0] 76543210 data r2 r1 r0 g2 g1 g0 b1 b0 [xvvd pin connection at non-palettized 8bpp/parallel mode] xvvd17161514131211109876543210 data r2 r1 r0 n c n c n c g2 g1 g0 n c n c n c b1 b0 n c n c n c n c [xvvd pin connection at non-palettized 8bpp/serial mode] xvvd 17 16 15 14 13 12 11 - 0 1 st data r2 r1 r0 n c n c n c nc
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-12 2 nd data g2 g1 g0 n c n c n c nc 3 rd data b1 b0 n c n c n c n c nc
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-13 4bpp display [bswp = 0, hwswp = 0] d[31:28] d[27:24] d[23:20] d[19:16] d[15:12] d[11:8] d[7:4] d[3:0] 000hp1p2p3p4p5p6p7p8 004h p9 p10 p11 p12 p13 p14 p15 p16 008h p17 p18 p19 p20 p21 p22 p23 p24 ... [bswp = 1, hwswp = 0] d[31:28] d[27:24] d[23:20] d[19:16] d[15:12] d[11:8] d[7:4] d[3:0] 000hp7p8p5p6p3p4p1p2 004h p15 p16 p13 p14 p11 p12 p9 p10 008h p23 p24 p21 p22 p19 p20 p17 p18 ... 2bpp display [bswp = 0, hwswp = 0] d [31:30] [29:28] [27:26] [25:24] [23:22] [21:20] [19:18] [17:16] 000hp1p2p3p4p5p6p7p8 004h p17 p18 p19 p20 p21 p22 p23 p24 008h p33 p34 p35 p36 p37 p38 p39 p40 ... d [15:14] [13:12] [11:10] [9:8] [7:6] [5:4] [3:2] [1:0] 000h p9 p10 p11 p12 p13 p14 p15 p16 004h p25 p26 p27 p28 p29 p30 p31 p32 008h p41 p42 p43 p44 p45 p46 p47 p48 ...
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-14 256 palette usage (tft) palette configuration and format control the S3C24A0 can support the 256 colors palette for various selection of color mapping. the user can select 256 colors from the 24-bit palette data through these three formats. 256 color palette consist of the 256(depth) 24-bit spsram. palette supports 6:6:6, 5:6:5(r:g:b), and 5:5:5:1(r:g:b:i) format. when the user use 5:5:5:1 format, the intensity data(i) is used as a common lsb bit of each rgb data. so, 5:5:5:1 format is same as (5+i):g(5+i):b(5+i) format. for example of 5:5:5:1 form at, write palette like table 28-4 and then connect vd pin to tft lcd panel(r(5+i)=vd[17:13]+vd[12], vd[6] or vd[0], g(5+i)=vd[11:7]+ vd[12], vd[6] or vd[0], b(5+i)=vd[5:1]+ vd[12], vd[6] or vd[0].) at the last, set palfrm register to 0x3. table 28-2. 6:6:6 palette data format index\bit pos. 23-181716151413121110 9 8 7 6 5 4 3 2 1 0 00h - r5r4r3r2r1r0g5g4g3g2g1g0b5b4b3b2b1b0 01h - r5r4r3r2r1r0g5g4g3g2g1g0b5b4b3b2b1b0 ....... - ?????????????????? ffh - r5r4r3r2r1r0g5g4g3g2g1g0b5b4b3b2b1b0 number of vd - 171615141312 1110 9 8 7 6 5 4 3 2 1 0 table 28-3. 5:6:5 palette data format index\bit pos. 23-161514131211109876543210 00h - r4r3r2r1r0g5g4g3g2g1g0b4b3b2b1b0 01h - r4r3r2r1r0g5g4g3g2g1g0b4b3b2b1b0 ....... - ???????????????? ffh - r4r3r2r1r0g5g4g3g2g1g0b4b3b2b1b0 number of vd - 17161514131110987654321 table 28-4. 5:5:5:1 palette data format index\bit pos. 23-161514131211109876543210 00h - r4r3r2r1r0g4g3g2g1g0b4b3 b2 b1 b0 i 01h - r4r3r2r1r0g4g3g2g1g0b4b3 b2 b1 b0 i ....... - ???????????????? ffh - r4r3r2r1r0g4g3g2g1g0b4b3b2b1b0 i number of vd - 171615141311109 8 7 5 4 3 2 1 1) notes: 1. vd12, vd6 and vd0 has same output value, i. 2. data[31:24] is invalid. palette read/write it is prohibited to access palette memory during the active status of the vstatus (vertical status) of lcdcon2 register. when the user going to do read/write operation on the palette, vstatus must be checked.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-15 1 2 3 4 5 lcd panel 16bpp 5:5:5+1 format(non-palette) a[31] a[30] a[29] a[28] a[27] a[26]a[25] a[24] a[23] a[22] a[21] a[20] a[19]a[18] a[17] a[16] r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i a[15] a[14] a[13] a[12] a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] r4 r3 r2 r1 r0 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 i 1 2 3 4 5 lcd panel 16bpp 5:6:5 format(non-palette) a[31] a[30] a[29] a[28] a[27] a[26]a[25] a[24] a[23] a[22] a[21] a[20] a[19]a[18] a[17] a[16] a[15] a[14] a[13] a[12]a[11] a[10] a[9] a[8] a[7] a[6] a[5] a[4] a[3] a[2] a[1] a[0] r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 r4 r3 r2 r1 r0 g5 g4 g3 g2 g1 g0 b4 b3 b2 b1 b0 figure 28-5. 16bpp display types
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-16 int_frsyn vsync hsync vden hsync vclk vd[17:0] (parallel mode) vbpd+1 vspw+1 vfpd+1 hbpd+1 vfpd+1 hspw+1 vden 1 frame 1 line lineval +1 hozval+1 vd[17:12] (serial mode) r g b r g b r ... b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b r g b figure 28-6. tft lcd timing example
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-17 virtual display the S3C24A0 supports hardware horizontal or vertical scrolling. if the screen is scrolled, the fields of lcdbaseu and lcdbasel registers need to be changed(refer to figure 28-7) but not the values of pagewidth and offsize. the size of video buffer in which the image is stored should be larger than lcd panel screen size. this is the data of line 1 of virtual screen. this is the data of line 1 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 11 of virtual screen. this is the data of line 11 of virtual screen. . . . before scrolling view port (the same size of lcd panel.) lineval + 1 offsize pagewidth this is the data of line 1 of virtual screen. this is the data of line 1 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 2 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 3 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 4 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 5 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 6 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 7 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 8 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 9 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 10 of virtual screen. this is the data of line 11 of virtual screen. this is the data of line 11 of virtual screen. . . . after scrolling lcdbaseu lcdbasel offsize figure 28-7. example of scrolling in virtual display
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-18 register description memory map table 28-5. configuration registers register address r/w description reset value lcdcon1 0x4a000000 r/w lcd control 1 0x00000000 lcdcon2 0x4a000004 r/w lcd control 2 0x00000000 lcdtcon1 0x4a000008 r/w lcd time control 1 0x00000000 lcdtcon2 0x4a00000c r/w lcd time control 2 0x00000000 lcdtcon3 0x4a000010 r/w lcd time control 3 0x00000000 lcdosd1 0x4a000014 r/w lcd osd control register 0x00000000 lcdosd2 0x4a000018 r/w foreground image(osd image) left top position set 0x00000000 lcdosd3 0x4a00001c r/w foreground image(osd image) right bottom position set 0x00000000 lcdsaddrb1 0x4a000020 r/w frame buffer start address 1(background buffer 1) 0x00000000 lcdsaddrb2 0x4a000024 r/w frame buffer start address 2(background buffer 2) 0x00000000 lcdsaddrf1 0x4a000028 r/w frame buffer start address 1(foreground buffer 1) 0x00000000 lcdsaddrf2 0x4a00002c r/w frame buffer start address 2(foreground buffer 2) 0x00000000 lcdeaddrb1 0x4a000030 r/w frame buffer end address 1(background buffer 1) 0x00000000 lcdeaddrb2 0x4a000034 r/w frame buffer end address 2(background buffer 2) 0x00000000 lcdeaddrf1 0x4a000038 r/w frame buffer end address 1(foreground buffer 1) 0x00000000 lcdeaddrf2 0x4a00003c r/w frame buffer end address 2(foreground buffer 2) 0x00000000 lcdvscrb1 0x4a000040 r/w virtual scr een offsize and pagewidth(background buffer 1) 0x 00000000 lcdvscrb2 0x4a000044 r/w virtual scr een offsize and pagewidth (background buffer 2) 0x 00000000 lcdvscrf1 0x4a000048 r/w virtual scr een offsize and pagewidth (foreground buffer 1) 0x 00000000 lcdvscrf2 0x4a00004c r/w virtual scr een offsize and pagewidth (foreground buffer 2) 0x 00000000 lcdintcon 0x4a000050 r/w lcd interrupt control 0x00000000 lcdkeycon 0x4a000054 r/w color key control 1 0x00000000 lcdkeyval 0x4a000058 r/w color key control 2 0x00000000 lcdbgcon 0x4a00005c r/w background color control 0x00000000 lcdfgcon 0x4a000060 r/w foreground color control 0x00000000 lcddithcon 0x4a000064 r/w lcd dithering control for active matrix 0x00000000 individual register descriptions lcd control 1 register register address r/w description reset value lcdcon1 0x4a000000 r/w lcd control 1 register 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-19 lcdcon1 bit description initial state burstlen [29:28] dma?s burst length selection : 00 : 16 word? burst 01 : 8 word? burst 10 : 4 word? burst 11 : reserved 0 reserved [27:22] reserved 0 bdbcon [21] active frame select control for background image. it will be adopted from next frame data. 0 = buffer1 1 = buffer2 0 fdbcon [20] active frame select control for foreground image(osd image). it will be adopted from next frame data. 0 = buffer1 1 = buffer2 0 diven [19] vclk divider( clkval ) counter enable control bit 0 = disable ( for power saving) 1 = enable 0 clkval [18:13] determine the rates of vclk and clkval[5:0]. vclk = hclk / [(clkval+1) x 2] ( clkval 0 ) 0 clkdir [12] select the clock source as direct or divide using clkval register. 0 = direct clock ( frequency of vclk = frequency of clock source) 1 = divided using clkval 0 reserved [11] this bit should be ?0? 0 pnrmode [10:9] select the display mode. 00 = rgb parallel mode ( rgb ) 01 = rgb parallel mode ( bgr ) 10 = rgb serial mode ( r->g->b) 11 = rgb serial mode ( b->g->r) 0 bppmodef [8:6] select the bpp (bits per pixel) mode for foreground image (osd). 011 = 8 bpp ( palettized ) 100 = 8 bpp ( non-palettized, r:3-g:3-b:2 ) 101 = 16 bpp ( non-palettized, r:5-g:6-b:5) 110 = 16 bpp ( non-palettized, r:5-g:5-b:5-i:1) 111 = unpacked 18 bpp ( non-palettized ) 0 bppmodeb [5:2] select the bpp (bits per pixel) mode for background image. 0000 = 1 bpp 0001 = 2 bpp 0010 = 4 bpp 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-20 0011 = 8 bpp ( palettized ) 0100 = 8 bpp ( non-palettized, r:3-g:3-b:2 ) 0101 = 16 bpp ( non-palettized, r:5-g:6-b:5) 0110 = 16 bpp ( non-palettized, r:5-g:5-b:5-i:1) 0111 = unpacked 18 bpp ( non-palettized ) 1xxx = reserved envid [1] lcd video output and the logic immediately enable/disable. 0 = disable the video output and the lcd control signal. 1 = enable the video output and the lcd control signal. 0 envid_f [0] lcd video output and the logic enable/disable at current frame end. 0 = disable the video output and the lcd control signal. 1 = enable the video output and the lcd control signal. * if you on and off this bit, then you will read ?h? and video controller is enabled until the end of current frame. 0 note) per frame video on-off : envid & envid_f on-off simultaneously. direct video on-off : envid on-off only. (where, envid_f = 0) lcd control 2 register register address r/w description reset value lcdcon2 0x4a000004 r/w lcd control 2 register 0x00000000 lcdcon2 bit description initial state linecnt (read only) [25:15] provide the status of the line counter (read only) up count from 0 to lineval 0 vstatus [14:13] vertical status (read only). 00 = vsync 01 = back porch 10 = active 11 = front porch 0 hstatus [12:11] horizontal status (read only). 00 = hsync 01 = back porch 10 = active 11 = front porch 0 palfrm [10:9] this bit determines the size of the palette data format 00 = reserved 01 = 18 bit ( 6:6:6) 10 = 16 bit (5:6:5) 11 = 16 bit ( 5:5:5:1) 0 reserved [8] this bit must be ?0?. 0 ivclk [7] this bit controls the polarity of the vclk active edge. 0 = the video data is fetched at vclk falling edge 1 = the video data is fetched at vclk rising edge 0 ihsync [6] this bit indicates the hsync pulse polarity. 0 = normal 1 = inverted 0 ivsync [5] this bit indicates the vsync pulse polarity. 0 = normal 1 = inverted 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-21 reserved [4] reserved 0 ivden [3] this bit indicates the vden signal polarity. 0 = normal 1 = inverted 0 bitswp [2] bit swap control bit. 0 = swap disable 1 = swap enable 0 bytswp [1] byte swap control bit. 0 = swap disable 1 = swap enable 0 hawswp [0] half-word swap control bit. 0 = swap disable 1 = swap enable 0 lcd time control 1 register register address r/w description reset value lcdtcon1 0x4a000008 r/w lcd control 2 register 0x00000000 lcdtcon1 bit description initial state vbpd [23:16] vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period. 0 vfpd [15:8] vertical front porch is the number of inactive lines at the end of a frame, before vertical synchronization period. 0 vspw [7:0] vertical sync pulse width determines the vsync pulse's sync level width by counting the number of inactive lines. 0 lcd time control 2 register register address r/w description reset value lcdtcon2 0x4a00000c r/w lcd time control 2 register 0x00000000 lcdtcon2 bit description initial state hbpd [23:16] horizontal back porch is the number of vclk periods between the falling edge of hsync and the start of active data. 0000000 hfpd [15:8] horizontal front porch is the number of vclk periods between the end of active data and the rising edge of hsync. 0x00 hspw [7:0] horizontal sync pulse width determines the hsync pulse's sync level width by counting the number of the vclk. 0x00 lcd time control 3 register register address r/w description reset value lcdtcon3 0x4a000010 r/w lcd time control 3 register 0x00000000 lcdtcon3 bit description initial state
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-22 lineval [21:11] these bits determine the vertical size of lcd panel. 0 hozval [10:0] these bits determine the horizontal size of lcd panel. 0 lcd osd control 1 register register address r/w description reset value lcdosd1 0x4a000014 r/w lcd osd control 1 register 0x00000000 lcdosd1 bit description initial state osden_f [9] osd(on-screen display) control bit. 0 = osd disable 1 = osd enable 0 osd_bld_pix [8] select blending mode 0 = per plane blending (8/16/18 bpp mode) 1 = per pixel blending (18 bpp only) 0 osd_alpha [7:0] 8-bit alpha value for per plane defined by equation 28-1. 0 note) osd_alpha when blending mode is per pixel should be written in msb 8 bits of d[31:0]. if color key is enabled, blending function is not performed. lcd osd control 2 register register address r/w description reset value lcdosd2 0x4a000018 r/w lcd osd control 2 register 0x0 lcdosd2 bit description initial state osd_lefttop_x [21:11] horizontal screen coordinate for left top pixel of osd image 0 osd_lefttop_y [10:0] vertical screen coordinate for left top pixel of osd image 0 lcd osd control 3 register register address r/w description reset value lcdosd3 0x4a00001c r/w lcd osd control 3 register 0x0 lcdosd3 bit description initial state osd_rightbot_x [21:11] horizontal screen c oordinate for right bottom pixel of osd image. osd_rightbot_x <= lcd panel size of x. 0 osd_rightbot_y [10:0] vertical screen coordinate for right bottom pixel of osd image. osd_rightbot_x <= lcd panel size of y. 0 note) horizontal screen coordinate of lcdosd2 and lcdosd3 must be in word boundary. so, 18 bpp mode can has x position by 1 pixel. ( ex, x = 0,1,2,3?.)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-23 16 bpp mode can has x position by 2 pixel. ( ex, x = 0,2,4,6?.) 8 bpp mode can has x position by 4 pixel. ( ex, x = 0,4,8,12?.) frame buffer start address registers register address r/w description reset value lcdsaddrb1 0x4a000020 r/w frame buffer start address register for background buffer 1 0x0 lcdsaddrb2 0x4a000024 r/w frame buffer start address register for background buffer 2 0x0 lcdsaddrf1 0x4a000028 r/w frame buffer start address register for foreground(osd) buffer 1 0x0 lcdsaddrf2 0x4a00002c r/w frame buffer start address register for foreground(osd) buffer 2 0x0 lcdsaddrxx bit description initial state lcdbank [31:24] these bits indicate a[31:24] of the bank location for the video buffer in the system memory. 0 lcdbaseu [23:0] these bits indicate a[23:0] of the start address of the lcd frame buffer. 0 frame buffer end address registers register address r/w description reset value lcdeaddrb1 0x4a000030 r/w frame buffer end address register for background buffer 1 0x0 lcdeaddrb2 0x4a000034 r/w frame buffer end address register for background buffer 2 0x0 lcdeaddrf1 0x4a000038 r/w frame buffer end address register for foreground(osd) buffer 1 0x0 lcdeaddrf2 0x4a00003c r/w frame buffer end address register for foreground(osd) buffer 2 0x0 lcdeaddrxx bit description initial state lcdbasel [23:0] these bits indicate a[23:0] of the end address of the lcd frame buffer. lcdbasel = lcdbaseu + (pagewidth+offsize) x (lineval+1) 0x0000 virtual screen offsize and pagewidth registers register address r/w description reset value
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-24 lcdvscrb1 0x4a000040 r/w virtual screen offsize and pagewidth for background buffer 1 0x00000000 lcdvscrb2 0x4a000044 r/w virtual screen offsize and pagewidth for background buffer 2 0x00000000 lcdvscrf1 0x4a000048 r/w virtual screen offsize and pagewidth for foreground(osd) buffer 1 0x00000000 lcdvscrf2 0x4a00004c r/w virtual screen offsize and pagewidth for foreground(osd) buffer 2 0x00000000 lcdvscrxx bit description initial state offsize [25:13] virtual screen offset size (the number of byte). this value defines the difference between the address of the last byte displayed on the previous lcd line and the address of the first byte to be displayed in the new lcd line. offsize must has value more than burst length value or 0. 0 pagewidth [12:0] virtual screen page width (the number of byte). this value defines the width of the view port in the frame. pagewidth must has value which is multiple of the burst length. 0 lcd interrupt control register register address r/w description reset value lcdintcon 0x4a000050 r/w indicate the lcd interrupt control register 0x0 lcdintcon bit description initial state framesel0 [11:10] lcd frame interrupt 2 at start of : 00 = back porch 01 = vsync 10 = active 11 = front porch 0 framesel1 [9:8] lcd frame interrupt 1 at start of : 00 = none 01 = back porch 10 = vsync 11 = front porch 0 intfrmen [7] lcd frame interrupt enable control bit. 0 = lcd frame interrupt disable 1 = lcd frame interrupt enable 0 reserved [6:5] reserved. 0 reserved [4:2] reserved. 0 reserved [1] reserved. 0 inten [0] lcd interrupt enable control bit. 0 = lcd interrupt disable 1 = lcd interrupt enable 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-25 color key 1 register register address r/w description reset value lcdkeycon 0x4a000054 r/w color key control register 0x00000 lcdkeycon bit description initial state keyen [25] color key (chroma key ) enable control 0 = color key disable, blending enable 1 = color key enable, blending disable 0 dircon [24] color key (chroma key)direction control 0 = if the pixel value match foreground image with colval according to compkey, pixel from background image is displayed (only in osd area) 1 = if the pixel value match background with colval according to compkey, pixel from foreground image is displayed (only in osd area) 0 compkey [23:0] each bit is correspond to the colval[23:0]. if some bit position is set then that bit position of colval and pixel value will not be compared. 0 color key 2 register register address r/w description reset value lcdcolval 0x4a000058 r/w color key value ( transparent value) register 0x00000000 lcdcolval bit description initial state colval [23:0] color key value for the transparent pixel effect. 0 note) colval and compkey use 24bit data at all bpp mode. 18 bpp mode : 18 bit color value is valid. colval 23 22 21 20 19 18 17-16 15 14 13 12 11 10 9-8 7 6 5 4 3 2 1- 0 data r5 r4 r3 r2 r1 r0 x g5 g4 g3 g2 g1 g0 x b5 b4 b3 b2 b1 b0 x x: don?t care, we recommend that those bits are filled with ?0?. compke y 23 22 21 20 19 18 17-16 15 14 13 12 11 10 9-8 7 6 5 4 3 2 1-0 data r5 r4 r3 r2 r1 r0 0x3 g5 g4 g3 g2 g1 g0 0x3 b5 b4 b3 b2 b1 b0 0x3 compkey[17:16], compkey[9: 8] and compkey[1:0] must be 0x3. 16 bpp (5:6:5) mode : 16 bit color value is valid
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-26 colval232221201918-161514131211109-8765432- 0 data r5 r4 r3 r2 r1 x g5 g4 g3 g2 g1 g0 x b5 b4 b3 b2 b1 x x: don?t care, we recommend that those bits are filled with ?0?. compke y 23 22 21 20 19 18-16 15 14 13 12 11 10 9-8 7 6 5 4 3 2-0 data r5 r4 r3 r2 r1 0x7 g5 g4 g3 g2 g1 g0 0x3 b5 b4 b3 b2 b1 0x7 compkey[18:16] and compkey[2:0] must be 0x7. compkey[ 9: 8] must be 0x3. compkey register must be set properly for the each bpp mode. background color map register address r/w description reset value lcdbgcon 0x4a00005c r/w background color control 0x00000 lcdbgcon bit description initial state bgcolen [24] background color mapping control bit . if this bit is enabled then lcd background dma will stop, and gbcolor will be appear on background image instead of original image. 0 = disable 1 = enable 0 bgcolor [23:0] color value 0 foreground color map register address r/w description reset value lcdfgcon 0x4a000060 r/w foreground color control 0x00000 lcdfgcon bit description initial state fgcolen [24] foreground color mapping control bit . if this bit is enabled then lcd foreground dma will stop, and fgcolor will be appear on foreground image instead of original image. 0 = disable 1 = enable 0 fgcolor [23:0] color value 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor lcd controller 28-27 dithering control 1 register register address r/w description reset value lcddithmode 0x4a000064 r/w dithering mode register. 0x00000 lcddithmode bit description initial state rdithpos [6:5] red dither bit control 01 : 6bit 1x : 5bit 0 gdithpos [4:3] green dither bit control 01 : 6bit 1x : 5bit 0 bdithpos [2:1] blue dither bit control 01 : 6bit 1x : 5bit 0 dithen [0] dithering enable bit 0 = dithering disable 1 = dithering enable 0 note ) dithering function can reduce the ?contouring? effect. the ?contouring? effect is a undesirable artifact which can be occurred at the following cases. - reduce quantization ( pre-view of camera image) - conversion of image data from yuv format to an rgb format - edge boosting ( rigid line of 3d image ) -etc. notice: lcd controller use fixed dithering matrix, and it can occur the side artifact known as ?graininess?. so, user must make decision by trade-off between contouring effect and graininess effect.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. lcd controller S3C24A0 risc microprocessor 28-28 background palette ram access address (not sfr) index address r/w description reset value 00 0x4a001000 r/w background palette entry 0 address undefined 01 0x4a001004 r/w background palette entry 1 address undefined --- - - ff 0x4a0013fc r/w background palette entry 255 address undefined foreground palette ram access address (not sfr) index address r/w description reset value 00 0x4a002000 r/w foreground palette entry 0 address undefined 01 0x4a002004 r/w foreground palette entry 1 address undefined --- - - ff 0x4a0023fc r/w foreground palette entry 255 address undefined
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor key pad 29-1 key pad i/f (preliminary) overview the key pad i/f in S3C24A0 receives the key matrix input s. an internal register remembers the last key pressed even after the key is released. it provides interrupt source and status register at the moment of key pressed or key released or both cases. the internal debouncing filter prevent the switching noises. the keydat register value is the number of the pressed ke y. the number of 25 key is same as figure 29-1. S3C24A0 keyif scan_x[0] scan_x[4] scan_y[0] scan_y[4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 figure 29-1. key matrix interface guide
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. key pad S3C24A0 risc microprocessor 29-2 keypad control register keypad control registers (keydat, keypup) register address r/w description reset value keydat 0x44900000 r/w the data register for keypad input 0x20 keydat bit description keydat[3:0] [4:0] keypad input decoding data (read only) keyval [5] keydat valid status (read only) 0 = valid 1 = invalid keyclear [6] key clear (write only) 0 = no action 1 = clear the keydat keyen [7] key enable 0 = disable 1= enable keypad interrupt control register register address r/w description reset value keyintc 0x44900004 r/w keypad input ports interrupt control 0x0 keyintc bit description keyintlv [2:0] keypad input ports interrupt level 000 = low level (key pressing) 001=high level(key not pressing) 010 = rising edge(key released) 10x=falling edge (key pressed) 11x = both edge(key released or key pressed) keyinten [3] interrupt enable of keypad input ports. 0 = disable 1= enable
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor key pad 29-3 debouncing filter filter_in filter_out width = filter_clk*(width_reg+1) keypad filter control register ( keyflt ) register address r/w description reset value keyflt0 0x44900008 r/w key pad input filter control register 0x0000 keyflt1 0x4490000c r/w key pad input filter control register 0x0000 keyflt0 bit description selclk [0] select filter clock 0 = rtc clock 1 = gclk filen [1] filter enable 0 = disable 1= enable reserved [15:2] must be ?0? keyflt1 bit description width_reg [13:0] filtering wi dth of keypad input ports. reserved [15:14] must be ?0?
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. key pad S3C24A0 risc microprocessor 29-4 keypad manual scan control register ( yman ) register address r/w description reset value keyman 0x44900010 r/w keypad manual scan control 0x1f yman bit description y_val [4:0] keypad manual column value. (read only) man_en [5] keypad manual scan control enable 0 = disable 1= enable
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor a/d converter and touch screen 30 -1 adc & touch screen interface (preliminary) overview the 10-bit cmos adc (analog to digital converter) of S3C24A0 is a recycling type device with 8-channel analog inputs. it converts the analog input si gnal into 10-bit binary digital codes at a maximum conversion rate of 500ksps with 2.5mhz a/d converter cl ock. a/d converter operates with on-chip sample-and-hold function and power down mode is supported. S3C24A0 supports touch screen interface. this function consists of touch screen panel, 4 internal sw itch, external voltage source , ain[7] and ain[5] (refer to the example, figure 30-2). touch screen interface is controlling and selecti ng control signal (nypon, ymon, nxpon and xmon) and analog pads (ain[7] and ain[5]) which are connected with pads of touch screen panel and the internal switch for x-position conversion and y-position conversion. touch screen interface contains switch control logic and adc interface logic with interrupt generation logic. features ? resolution : 10-bit ? differential linearity error : 1.0 lsb ? integral linearity error : 2.0 lsb ? maximum conversion rate : 500 ksps ? low power consumption ? internal switch for x-position conversion and y-position conversion ? power supply voltage : 3.3v ? analog input range : 0 ~ 3.3v ? on-chip sample-and-hold function ? normal conversion mode ? separate x/y position conversion mode ? auto(sequential) x/y position conversion mode ? waiting for interrupt mode (stylus pen up or down interrupt)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. a/d converter and touch screen S3C24A0 risc microprocessor 30-2 adc & touch screen interface operation block diagram figure 30-1 shows the functional block diagram of s3c24a 0 a/d converter and touch screen interface. note that the a/d converter devic e is a recycling type. a pull-up resister is attached to ain[7] on vdda _adc. so, xp pad of touch screen panel should be connected with ain[7] of S3C24A0 and yp pad of touc h screen panel should be connected with ain[5]. 8:1 mux a/d converter adc interface &touch screen controller vssa_adc waiting for interrupt int_penup int_adc adc input control interrup generation ain[7] ain [6] ain [5] ain [4] vdda_adc xmon nxpon ymon nypon ain [3] ain [2] ain [1] ain [0] internal transister control int_pendn switch matrix figure 30-1. adc and touch screen interface functional block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor a/d converter and touch screen 30 -3 example for touch screen in this example, ain[7] is connected with xp and ain[5] is connected with yp pad of touch screen panel. to control pads of touch screen panel (xp, xm, yp and ym), 4 internal transistor are applied and control signals, nypon, ymon, nxpon and xmon are connected with 4 internal transistor. internal transistor control vdda_adc xm yp ym a[7] a[5] xmon nxpon y mon nypon touch panel S3C24A0 a[6] a[4] xp figure 30-2. example of adc and touch screen interface 1. select separate x/y position conversion mode or auto (sequential) x/y position conversion mode to get x/y position. 2. set touch screen interface to waiting interrupt mode, 3. if interrupt occurs, then appropriate conversion (separ ate x/y position conversion mode or auto (sequential) x/y position conversion mode) is activated. 4. after get the proper value about x/y positi on, return to waiting for interrupt mode.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. a/d converter and touch screen S3C24A0 risc microprocessor 30-4 function descriptions a/d conversion time when the pclk frequency is 50mhz and the prescaler value is 49, total 10-bit conversion time is as follows. a/d converter freq. = 50mhz/(49+1) = 1mhz conversion time = 1/(1mhz / 5cycles) = 1/200khz = 5 us note: this a/d converter was designed to operate at maximum 2. 5mhz clock, so the conversion rate can go up to 500 ksps. touch screen interface mode 1. normal conversion mode normal conversion mode (auto_pst = 0, xy_pst = 0) is the most likely used for general purpose adc conversion. this mode can be initialized by setting the adccon and adctsc and completed with a read the xpdata (normal adc) value of adcdax (adc data register 0). 2. separate x/y position conversion mode touch screen controller can be operated by one of two conversion modes. separate x/y position conversion mode is operated as the following way; x-position mode (auto_pst = 0 and xy_pst = 1) writes x-position conversion data to xpdata of adcdax register, after conversion, touch screen in terface generates the interrupt source (int_adc) to interrupt controller. y-position mode (auto_pst = 0 and xy_pst = 2) writes y-position conversion data to ypdata of adcday, after conversion, touch screen interface gener ates the interrupt source (int_adc) to interrupt controller also. table 30-1. condition of touch screen panel pads in separate x/y position conversion mode. xp xm yp ym x position conversion vdda_adc gnd ain[5] hi-z y position conversion ain[7] hi-z vdda_adc gnd
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor a/d converter and touch screen 30 -5 1. auto(sequential) x/y position conversion mode auto (sequential) x/y position conversion mode (a uto_pst = 1 and xy_pst = 0) is operated as the following; touch screen controller automatically converts x-position and y-position. touch screen controller writes x- measurement data to xpdata of adcdax, and then wr ites y-measurement data to ypdata of adcday. after auto (sequential) position conversion, touch sc reen controller is generating interrupt source(int_adc) to interrupt controller. table 30-2. condition of touch screen panel pads in auto (sequential) x/y position conversion mode. xp xm yp ym x position conversion vdda_adc gnd ain[5] hi-z y position conversion ain[7] hi-z vdda_adc gnd 1. waiting for interrupt mode when touch screen controller is in waiting for inte rrupt mode (ym_sen = 1, xp_sen = 1 and xy_pst = 3), touch screen controller is waiting for stylus down or up. touch screen controller is generating interrupt (int_pendn or int_penup) signal when the st ylus is down or up on touch screen panel. after interrupt occurs, x and y position can be read by the proper conversion mode (separate x/y position conversion mode or auto x/y position conversion mode). table 30-3. condition of touch screen panel pads in waiting for interrupt mode. xp xm yp ym waiting for interrupt mode ain[7](pull-up enable) hi-z ain[5] gnd standby mode standby mode is activated when stdbm of adccon register is set to '1'. in this mode, a/d conversion operation is halted and xpdata (normal adc) of adcdax and ypdat a of adcday contain the previous converted data.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. a/d converter and touch screen S3C24A0 risc microprocessor 30-6 programming notes 1. the a/d converted data can be acce ssed by means of interrupt or po lling method. with interrupt method the overall conversion time - from a/d converter st art to converted data read - may be delayed because of the return time of interrupt service routine and dat a access time. with polling method, by checking the adccon[15] - end of conversion flag-bit, the read time from adcdat register can be determined. 2. another way for starti ng a/d conversion is provided. after adccon[1] - a/d conversion start-by-read mode-is set to 1, a/d conversion starts simultaneously whenever c onverted data is read. xp a x-conversion yp b y-conversion c d = delay value of adcdly register a = d x (1/x-tal clock) or a = d x (1/external clock) b = d x (1/pclk) c = d x (1/pclk) stylus down stylus up figure 30-3 timing diagram at auto (se quential) x/y position conversion mode
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor a/d converter and touch screen 30 -7 adc and touch screen interface special registers adc control register (adccon) register address r/w description reset value adccon 0x4580_0000 r/w adc control register 0x3fc4 adccon bit description initial state ecflg [15] end of conversion flag(read only) 0 = a/d conversion in process 1 = end of a/d conversion 0 prscen [14] a/d converter prescaler enable 0 = disable 1 = enable 0 prscvl [13:6] a/d converter prescaler value data value: 1 ~ 255 note: adc freqeuncy should be set less than pclk by 5times. (ex. pclk=10mhz, adc freq. < 2mhz) 0xff sel_mux [5:3] analog input channel select 000 = ain 0 001 = ain 1 010 = ain 2 011 = ain 3 100 = ain 4 101 = ain 5 (yp) 110 = ain 6 111 = ain 7 (xp) 0 stdbm [2] standby mode select 0 = normal operation mode 1 = standby mode 1 read_ start [1] a/d conversion start by read 0 = disable start by read operation 1 = enable start by read operation 0 enable_start [0] a/d conversion starts by setting this bit. if read_start is enabled, this value is not valid. 0 = no operation 1 = a/d conversion starts and this bit is cleared after the start-up. 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. a/d converter and touch screen S3C24A0 risc microprocessor 30-8 adc touch screen control register (adctsc) register address r/w description reset value adctsc 0x4580_0004 r/w adc touch screen control register 0x058 adctsc bit description initial state reserved [11:8] reserved. should be set to 0. 0 ym_sen [7] select output value of ymon 0 = ymon output is 0. (ym = hi-z) 1 = ymon output is 1. (ym = gnd) 0 yp_sen [6] select output value of nypon 0 = nypon output is 0. (yp = external voltage) 1 = nypon output is 1. (yp is connected with ain[5]) 1 xm_sen [5] select output value of xmon 0 = xmon output is 0. (xm = hi-z) 1 = xmon output is 1. (xm = gnd) 0 xp_sen [4] select output value of nxpon 0 = nxpon output is 0. (xp = external voltage) 1 = nxpon output is 1. (xp is connected with ain[7]) 1 pull_up 1) [3] pull-up switch enable 0 = xp pull-up enable. 1 = xp pull-up disable. 1 auto_pst 2) [2] automatically sequencing conver sion of x-position and y-position 0 = normal adc conversion. 1 = auto (sequential) x/y position conversion mode. 0 xy_pst 3) [1:0] manually measurement of x-position or y-position. 00 = no operation mode 01 = x-position measurement 10 = y-position measurement 11 = waiting for interrupt mode 0 note: 1. unexpected pen-up or pen-down interrupt may be occu rred when pull-up switch is turn on. it is recommended that pull-up enable switch is turn on before setting to t he waiting for interrupt mode because some stabilization time of pull-up switch is needed. 2. auto_pst bit should be set whenever the data conv ersion ends if the conversion start by read mode is activated. 3. when all data conversions are finished at automatic ally sequencing conversion m ode, the conversion pointer remained at y position conversion mode. it is re commended to set xy_pst register to ?01? (x-position measurement mode) every conversion time for getting right result.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor a/d converter and touch screen 30 -9 adc start delay register (adcdly) register address r/w description reset value adcdly 0x4580_0008 r/w adc start or interval delay register 0x00ff adcdly bit description initial state delay [15:0] 1) normal conversion mode, separ ate x/y position conversion mode, auto (sequential) x/y position conversion mode. x/y position conversion delay value. 2) waiting for interrupt mode. when stylus down occurs at wait ing for interrupt mode, generates interrupt signal (int_adc), having in terval (several ms), for auto x/y position conversion. note) don?t use zero value(0x0000) 00ff note: 1. before adc conversion, touch screen uses x-ta l clock or extclk (waiting for interrupt mode). 2. during adc conversion pclk is used.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. a/d converter and touch screen S3C24A0 risc microprocessor 30-10 adc conversion data register (adcdax) register address r/w description reset value adcdax 0x4580_000c r adc conversion data register x-position conversion data at touch screen mode - adcdax bit description initial state updown [15] up or down state of stylus at waiting for interrupt mode. 0 = stylus down state. 1 = stylus up state. - auto_pst [14] automatic sequencing conversion of x-position and y-position 0 = normal adc conversion. 1 = sequencing measurement of x-position, y-position. - xy_pst [13:12] manually measurement of x-position or y-position. 00 = no operation mode 01 = x-position measurement 10 = y-position measurement 11 = waiting for interrupt mode - reserved [11:10] reserved xpdata (normal adc) [9:0] x-position conversion data value (include normal adc conversion data value) data value : 0 ~ 3ff -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor a/d converter and touch screen 30 -11 adc conversion data register (adcday) register address r/w description reset value adcday 0x4580_0010 r adc conversion data register y-position conversion data at touch screen mode - adcday bit description initial state updown [15] up or down state of stylus at waiting for interrupt mode. 0 = stylus down state. 1 = stylus up state. - auto_pst [14] automatically sequencing conversion of x-position and y-position 0 = normal adc conversion. 1 = sequencing measurement of x-position, y-position. - xy_pst [13:12] manually measurement of x-position or y-position. 00 = no operation mode 01 = x-position measurement 10 = y-position measurement 11 = waiting for interrupt mode - reserved [11:10] reserved ypdata [9:0] y-position conversion data value data value : 0 ~ 3ff -
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. a/d converter and touch screen S3C24A0 risc microprocessor 30-12 notes
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-1 secure digital interface overview the S3C24A0 sdi(secure digital interface) can interface for sd memory card, sdio device and mmc(multi- media card). feature sd memory card spec(ver 1.0) / mmc spec(2.11) compatible sdio card spec(ver 1.0) compatible 16 words(64 bytes) fifo for data tx/rx 40-bit command register 136-bit response register 8-bit prescaler logic(freq = system clock / (p + 1)) normal, and dma data transfer mode(byte, halfword , word transfer) dma burst4 access support(only word transfer) 1bit / 4bit(wide bus) mode & block / stream mode switch support
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdi S3C24A0 risc microprocessor 31-2 block diagram cmd reg (5byte) resp reg (17byte) cmd control 8bit shift reg crc7 prescaler fifo (64byte) dat control 32bit shift reg crc16*4 dma int apb i/f 8 8 8 8 32 32 32 32 32 32 paddr psel pclk pwdata [31:0] prdata [31:0] dreq dack int txcmd rxcmd sdclk txdat[3:0] rxdat[3:0] figure 31-1. sdi block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-3 sdi operation a serial clock line synchronizes shifting and sampling of t he information on the five data lines. the transmission frequency is controlled by making the appropriate bit setti ngs to the sdipre register. you can modify its frequency to adjust the baud rate data register value. programming procedure (common) to program the sdi modules, follow these basic steps: 1. set sdicon to configure properly with clock & interrupt enable 2. set sdipre to configure with a proper value. 3. wait 74 sdclk clock cycle in order to initialize the card. cmd path programming 1. write command argument 32bit to sdicarg. 2. determine command types and start command transmit with setting sdiccon. 3. confirm the end of sdi cmd path operat ion when the specific flag of sdicsta is set 4. the flag is cmdsent if command type is no response. 5. the flag is rspfin if command type is with response. 6. clear the corresponding flag of sdicsta through writing one with this bit dat path programming 1. write data timeout period to sdidtimer. 2. write block size(block length) to sdibsize(normally 0x80 word). 3. determine the mode of block, wide bus, dma, etc and start data transfer with setting sdidcon. 4. tx data write data to data register(sdidat) while tx fifo is available(tfdet is set), or half(tfhalf is set), or empty(tfempty is set). 5. rx data read data from data register(sdidat) while rx fifo is available(rfdet is set), or full(rffull is set), or half(rfhalf is set), or ready for last data(rflast is set). 6. confirm the end of sdi dat path operat ion when datfin flag of sdidsta is set 7. clear the corresponding flag of sdidsta through writing one with this bit
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdi S3C24A0 risc microprocessor 31-4 sdio operation there are two functions of sdio operation: sdio in terrupt receiving and read wait request generation. these two functions can operate when rcvioint bit and rwaiten bit of sdicon register is acti vated respectively. and two functions have the steps and conditions like below. sdio interrupt in sd 1bit mode, interrupt is received through all range from rxdat [1] pin. in sd 4bit mode, rxdat[1] pin is shared between data receiving and interrupt receiving. when interrupt detection range (interrupt period) is: 1. single block : the time between a and b - a : 2clocks after the completion of a data packet - b : the completion of sending the en d bit of the next withdata command 2. multi block, prdtype = 0 : the time between a and b, restart at c - a : 2clocks after the completion of a data packet - b : 2clocks after a - c : 2clocks after the end bit of the abort command response 3. multi block, prdtype = 1 : the time between a and b, restart at a - a : 2clocks after the completion of a data packet - b : 2clocks after a - in case of last block, interrupt period begins at a, but not ends at b(cmd53 case) read wait request regardless of 1bit or 4bit mode, read wait request signal transmits to tx dat[2] pin in condition of below. - in read multiple operation, request signal transm ission begins at 2clocks after the end of the data block - transmission ends when user sets to one rwaitreq bit of sdidsta register
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-5 sdi special registers sdi control register (sdicon) register address r/w description reset value sdicon 0x4600_0000 r/w sdi control register 0x0 sdicon bit description initial value reserved [31:9] sdmmc reset (sdreset) [8] reset whole sdmmc block. this bit is automatically clear. 0 = normal mode, 1 = sdmmc reset 0 hold margin (holdmgn) [7:6] determines how much you delay cmd, dat lines for hold margin in mmc clock type 00 = 1/2 pclk cycle, 01 = 1 pclk cycle 10 = 3/2 pclk cycles, 11 = 2 pclk cycles 0 clock type (ctyp) [5] determines which clock type is used as sdclk. 0 = sd type, 1 = mmc type 0 byte order type(byteorder) [4] determines byte order type when you read(write) data from(to) sd host fifo with word boundary. 0 = type a, 1 = type b 0 receive sdio interrupt from card (rcvioint) [3] determines whether sd host receives sdio interrupt from the card or not(for sdio). 0 = ignore, 1 = receive sdio interrupt 0 read wait enable(rwaiten) [2] determines read wait request signal generate when sd host waits the next block in multiple block read mode. this bit needs to delay the next block to be transmitted from the card(for sdio). 0 = disable(no generate), 1 = read wait enable(use sdio) 0 reserved [1] clock out enable (enclk) [0] determines whether sdclk out enable or not 0 = disable(prescaler off), 1 = clock enable 0 * byte order type - type a: (access by word) d[7:0] d[15:8] d[23:16] d[31:24] (access by halfword) d[7:0] d[15:8] - type b: (access by word) d[31:24] d[23:16] d[15:8] d[7:0] (access by halfword) d[15:8] d[7:0] sdi baud rate prescaler register (sdipre) register address r/w description reset value sdipre 0x4600_0004 r/w sdi buad rate prescaler register 0x01 sdipre bit description initial value prescaler value [7:0] determines sdi clock (sdclk) rate as above equation. baud rate = pclk / (prescaler value + 1) 0x01 * prescaler value should be greater than zero.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdi S3C24A0 risc microprocessor 31-6 sdi command argument register (sdicarg) register address r/w description reset value sdicarg 0x4600_0008 r/w sdi command argument register 0x0 sdicarg bit description initial value cmdarg [31:0] command argument 0x00000000 sdi command control register (sdiccon) register address r/w description reset value sdiccon 0x4600_000c r/w sdi command control register 0x0 sdiccon bit description initial value reserved [31:13] abort command (abortcmd) [12] determines whether command type is for abort(for sdio). 0 = normal command, 1 = abort command(cmd12, cmd52) 0 command with data (withdata) [11] determines whether command type is with data(for sdio). 0 = without data, 1 = with data 0 longrsp [10] determines whether host receives a 136-bit long response or not 0 = short response, 1 = long response 0 waitrsp [9] determines whether host waits for a response or not 0 = no response, 1 = wait response 0 command start(cmst) [8] determines whether command operation starts or not. . this bit is automatically clear 0 = command ready, 1 = command start 0 cmdindex [7:0] command index with start 2bit(8bit) 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-7 sdi command status register (sdicsta) register address r/w description reset value sdicsta 0x4600_0010 r/(c) sdi command status register 0x0 sdicsta bit description initial value reserved [31:13] response crc fail(rspcrc) [12] r/c crc check failed when command response received. this flag is cleared by setting to one this bit. 0 = not detect, 1 = crc fail 0 command sent (cmdsent) [11] r/c command sent(not concerned with response). this flag is cleared by setting to one this bit. 0 = not detect, 1 = command end 0 command time out (cmdtout) [10] r/c command response timeout(64clk). this flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout 0 response receive end (rspfin) [9] r/c command response received. this flag is cleared by setting to one this bit. 0 = not detect, 1 = response end 0 cmd line progress on (cmdon) [8] command transfer in progress 0 = not detect, 1 = in progress 0 rspindex [7:0] response index 6bit with start 2bit(8bit) 0x00 sdi response register0 (sdirsp0) register address r/w description reset value sdirsp0 0x4600_0014 r sdi response register 0 0x0 sdirsp0 bit description initial value response0 [31:0] card status[31:0]( short), card status[127:96](long) 0x00000000 sdi response register1 (sdirsp1) register address r/w description reset value sdirsp1 0x4600_0018 r sdi response register 1 0x0 sdirsp1 bit description initial value rcrc7 [31:24] crc7(with end bit, shor t), card status[95:88](long) 0x00 response1 [23:0] unused(short), card status[87:64](long) 0x000000 sdi response register2 (sdirsp2) register address r/w description reset value sdirsp2 0x4600_001c r sdi response register 2 0x0 sdirsp2 bit description initial value response2 [31:0] unused(short), card status[63:32](long) 0x00000000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdi S3C24A0 risc microprocessor 31-8 sdi response register3 (sdirsp3) register address r/w description reset value sdirsp3 0x4600_0020 r sdi response register 3 0x0 sdirsp3 bit description initial value response3 [31:0] unused(short), card status[31:0](long) 0x00000000 sdi data / busy timer register (sdidtimer) register address r/w description reset value sdidtimer 0x4600_0024 r/w sdi data / busy timer register 0x0 sdidtimer bit description initial value reserved [31:21] datatimer [22:0] data / busy timeout period(0~2m cycle) 0x10000 sdi block size register (sdibsize) register address r/w description reset value sdibsize 0x4600_0028 r/w sdi block size register 0x0 sdibsize bit description initial value reserved [31:12] blksize [11:0] block size value(0~4095 byte) , don?t care when stream mode 0x000 * in case of multi block, blksize must be aligned to word (4byte) size. (blksize[1:0] = 00)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-9 sdi data control register (sdidcon) register address r/w description reset value sdidcon 0x4600_002c r/w sdi data control register 0x0 sdidcon bit description initial value reserved [31:25] burst4 enable (burst4) [24] enable burst4 mode in dma mode. this bit should be set only when data size is word. 0 = disable, 1 = burst4 enable 0 data size (datasize) [23:22] indicates the size of the transfer with fifo, which is typically byte, halfword or word. 00 = byte transfer, 01 = halfword transfer 10 = word transfer, 11 = reserved 0 sdio interrupt period type (prdtype) [21] determines whether sdio interrupt period is 2 cycle or extend more cycle when last data block is transferred(for sdio). 0 = exactly 2 cycle, 1 = more cycle(likely single block) 0 transmit after response (tarsp) [20] determines when data transmit start after response receive or not 0 = directly after datmode set, 1 = after response receive(assume datmode sets to 2?b11) 0 receive after command (racmd) [19] determines when data receive start after command sent or not 0 = directly after datmode set, 1 = after command sent (assume datmode sets to 2?b10) 0 busy after command (bacmd) [18] determines when busy receive start after command sent or not 0 = directly after datmode set, 1 = after command sent (assume datmode sets to 2?b01) 0 block mode (blkmode) [17] data transfer mode 0 = stream data transfer, 1 = block data transfer 0 wide bus enable (widebus) [16] determines enable wide bus mode 0 = standard bus mode(only sdidat[0] used), 1 = wide bus mode(sdidat[3:0] used) 0 dma enable (endma) [15] enable dma 0 = disable(polling), 1 = dma enable 0 data transfer start(dtst) [14] determines whether data transfer start or not. . this bit is auto- matically clear 0 = data ready, 1 = data start 0 data transfer mode (datmode) [13:12] determines which direction of data transfer 00 = no operation, 01 = only busy check start 10 = data receive start, 11 = data transmit start 00 blknum [11:0] block number(0~4095), don?t care when stream mode 0x000 * if you want one of tarsp, racmd, bacmd bits (s didcon [20:18]) to ?1?, you need to write on sdidcon register ahead of on sdiccon register. (always need for sdio)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdi S3C24A0 risc microprocessor 31-10 sdi data remain counter register (sdidcnt) register address r/w description reset value sdidcnt 0x4600_0030 r sdi data remain counter register 0x0 sdidcnt bit description initial value reserved [31:24] blknumcnt [23:12] remaining block number 0x000 blkcnt [11:0] remaining data byte of 1 block 0x000 sdi data status register (sdidsta) register address r/w description reset value sdidsta 0x4600_0034 r/(c) sdi data status register 0x0 sdidsta bit description initial value reserved [31:12] no busy(nobusy) [11] r/c busy is not active during 16cycle after cmd packet transmitted in only busy check mode. this flag is cleared by setting to 1 this bit. 0 = not detect, 1 = no busy signal 0 read wait request occur (rwaitreq) [10] r/c read wait request signal transmits to sd card. the request signal is stopped and this flag is cleared by setting to one this bit. 0 = not occur, 1 = read wait request occur 0 sdio interrupt detect(iointdet) [9] r/c sdio interrupt detect. this flag is cleared by setting to one this bit. 0 = not detect, 1 = sdio interrupt detect 0 reserved [8] crc status fail(crcsta) [7] r/c crc status error when data block sent(crc check failed). this flag is cleared by setting to one this bit. 0 = not detect, 1 = crc status fail 0 data receive crc fail(datcrc) [6] r/c data block received error(crc check failed). this flag is cleared by setting to one this bit. 0 = not detect, 1 = receive crc fail 0 data time out(dattout) [5] r/c data / busy receive timeout. this flag is cleared by setting to one this bit. 0 = not detect, 1 = timeout 0 data transfer finish(datfin) [4] r/c data transfer completes (data counter is zero). this flag is cleared by setting to one this bit. 0 = not detect, 1 = data finish detect 0 busy finish (busyfin) [3] r/c only busy check finish. this flag is cleared by setting to one this bit 0 = not detect, 1 = busy finish detect 0 reserved [2] 0 tx data progress on(txdaton) [1] data transmit in progress 0 = not active, 1 = data tx in progress 0 rx data progress on(rxdaton) [0] data receive in progress 0 = not active, 1 = data rx in progress 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-11 sdi fifo status register (sdifsta) register address r/w description reset value sdifsta 0x4600_0038 r sdi fifo status register 0x0 sdifsta bit description initial state reserved [31:16] fifo reset(frst) [16] c reset fifo value. this bit is automatically clear. 0 = normal mode, 1 = fifo reset 0 fifo fail error (fffail) [15:14] r/c fifo fail error when fifo occurs overrun / underrun data saving. this flag is cleared by setting to one these bits. 00 = not detect, 01 = fifo fail 10 = fifo fail in the last transfer(only fifo reset need) 11 = reserved 0 fifo available detect for tx (tfdet) [13] this bit indicates that fifo data is available for transmit when datmode is data transmit mode. if dma mode is enable, sd host requests dma operation. 0 = not detect(fifo full), 1 = detect(0 fifo 63) 0 fifo available detect for rx (rfdet) [12] this bit indicates that fifo data is available for receive when datmode is data receive mode. if dma mode is enable, sd host requests dma operation. 0 = not detect(fifo empty), 1 = detect(1 fifo 64) 0 tx fifo half full (tfhalf) [11] this bit sets to 1 whenever tx fifo is less than 33byte. 0 = 33 tx fifo 64, 1 = 0 tx fifo 32 0 tx fifo empty (tfempty) [10] this bit sets to 1 whenever tx fifo is empty. 0 = 1 tx fifo 64, 1 = empty(0byte) 0 rx fifo last data ready (rflast) [9] r/c this bit sets to 1 when rx fifo occurs to behave last data of all block. this flag is cleared by setting to one this bit. 0 = not received yet, 1 = rx fifo gets last data 0 rx fifo full (rffull) [8] this bit sets to 1 whenever rx fifo is full. 0 = 0 rx fifo 63, 1 = full(64byte) 0 rx fifo half full (rfhalf) [7] this bit sets to 1 whenever rx fifo is more than 31byte. 0 = 0 rx fifo 31, 1 = 32 rx fifo 64 0 fifo count (ffcnt) [6:0] number of data(byte) in fifo 0000000 * although the last rx data size is lager than remained count of fifo data, you could read this data. if this event happens, you should clear fffail field, and fifo reset field
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. sdi S3C24A0 risc microprocessor 31-12 sdi interrupt mask register (sdiimsk) register address r/w description reset value sdiimsk 0x4600_003c r/w sdi interrupt mask register 0x0 sdicon bit description initial value reserved [31 : 19] nobusy interrupt enable (nobusyint) [18] determines sdi generate an interrupt if busy signal is not active 0 = disable, 1 = interrupt enable 0 rspcrc interrupt enable (rspcrcint) [17] determines sdi generate an interrupt if response crc check fails 0 = disable, 1 = interrupt enable 0 cmdsent interrupt enable (cmdsentint) [16] determines sdi generate an interrupt if command sent(no response required) 0 = disable, 1 = interrupt enable 0 cmdtout interrupt enable (cmdtoutint) [15] determines sdi generate an interrupt if command response timeout occurs 0 = disable, 1 = interrupt enable 0 rspend interrupt enable (rspendint) [14] determines sdi generate an interrupt if command response received 0 = disable, 1 = interrupt enable 0 rwaitreq interrupt enable (rwreqint) [13] determines sdi generate an interrupt if read wait request occur. 0 = disable, 1 = interrupt enable 0 iointdet interrupt enable (intdetint) [12] determines sdi generate an interrupt if sd host receives sdio interrupt from the card(for sdio). 0 = disable, 1 = interrupt enable 0 fffail interrupt enable (fffailint) [11] determines sdi generate an interrupt if fifo fail error occurs 0 = disable, 1 = interrupt enable 0 crcsta interrupt enable (crcstaint) [10] determines sdi generate an interrupt if crc status error occurs 0 = disable, 1 = interrupt enable 0 datcrc interrupt enable (datcrcint) [9] determines sdi generate an interrupt if data receive crc failed 0 = disable, 1 = interrupt enable 0 dattout interrupt enable (dattoutint) [8] determines sdi generate an interrupt if data receive timeout occurs 0 = disable, 1 = interrupt enable 0 datfin interrupt enable (datfinint) [7] determines sdi generate an interrupt if data counter is zero 0 = disable, 1 = interrupt enable 0 busyfin interrupt enable(busyfinint) [6] determines sdi generate an interrupt if only busy check completes 0 = disable, 1 = interrupt enable 0 reserved [5] 0 tfhalf interrupt enable (tfhalfint) [4] determines sdi generate an interrupt if tx fifo fills half 0 = disable, 1 = interrupt enable 0 tfempty interrupt enable(tfemptint) [3] determines sdi generate an interrupt if tx fifo is empty 0 = disable, 1 = interrupt enable 0 rflast interrupt enable (rflastint) [2] determines sdi generate an interrupt if rx fifo has last data 0 = disable, 1 = interrupt enable 0 rffull interrupt enable (rffullint) [1] determines sdi generate an interrupt if rx fifo fills full 0 = disable, 1 = interrupt enable 0 rfhalf interrupt enable (rfhalfint) [0] determines sdi generate an interrupt if rx fifo fills half 0 = disable, 1 = interrupt enable 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor sdi 31-13 sdi data register (sdidatn) register address r/w description reset value sdidat0 0x4600_0040(w,hw,b) r/w sdi data0 register 0x0 sdidat1 0x4600_0044(word) r/w sdi data1 register 0x0 sdidat2 0x4600_0048(word) r/w sdi data2 register 0x0 sdidat3 0x4600_004c(word) r/w sdi data3 register 0x0 sdidatn bit description initial state data register [31:0] this field contains t he data to be transmitted or received over the sdi channel 0x00000000 * in case that dma burst4 mode is enabled by setting sdidcon [24], sdidat1 ~ sdidat3 are valid.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor memory stick 32-1 memory stick (preliminary) overview there are so many types of media for storing and tr ansferring data. memory stick is one of the popular media. the S3C24A0 supports memory stick specifications vers ion 1.3. four pins are dedicated for memory stick interface, which are bus state (ms_bs), serial data (ms_sdio), serial clock (ms_sclk) and insertion detect (ms_ins). features _ protocol is stared by writing to the command register (tp_cmd) _ supports dma _ busy timeout period can be controlled by setting the bsycnt bit fields in control status register (ctrl_sta) _ 16-bit access _ the output from fifo is only little endian _ built in 8-byte (2-word) fifo buffers for tx and rx respectively _ built in crc circuit (can be turned on/ off) _ pclk must be under 80mhz _ supports automatic command execution (can be turn on/ off) _ supports memory stick detection interrupt
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. memory stick S3C24A0 risc microprocessor 32-2 memory stick protocol figure 32-1and 2 shows the read/ write packet of memory stick. the memory stick host controller uses only pclk as its source clock. the ms_sclk frequency is made by divi ded pclk (1/1, 1/2, 1/4 or 1/8) and it is slower than 20mhz. bs0 bs1 bs2 bs3 bs0 in t tp c data cr c rdy/bsy in t memory stick host memory stick figure 32-1. memory stick write packet bs0 bs1 bs2 bs3 bs0 in t tp c data cr c rdy/bsy in t memory stick host memory stick figure 32-2. memory stick read packet mandatory hardware configuration the ms_sdio pin should be configured pull down resist or and the ms_ins pin should be configured pull up resistor.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor memory stick 32-3 host block pin description pin name function name dir active description xint interrupt request out low interrupt request signal line low level during interrupt request high level at access to intdatareg pi input parallel port in - parallel port for input only (used for insertion/extraction detect of memory stick) fixed in a high level when unused rbe receive buffer empty out high high level when receive data buffer is empty low level when there is data in receive data buffer rbf receive buffer full out high high level when receive data buffer is full. low level when there is space in receive data buffer tbe transmit buffer empty out high high level when transmit data buffer is empty low level when there is data in transmit data buffer tbf transmit buffer full out high high level when transmit data buffer is full low level when there is space in transmit data buffer nocrc int_p_end(ro) sdio interrupt control int_sif(ro) int_toe(ro) int_crc(ro) ins ins_en ins_inten xint rbf(ro) rbe(ro) tbf(ro) tbe(ro) fifo control fifo_int int_ins(ro) pi sien host controller bs sclk int_sta check int_en
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. memory stick S3C24A0 risc microprocessor 32-4 memory stick special registers prescaler control (mspre) register register address r/w description reset value mspre 0x46100000 r/w pescaler control register 0x0 mspre bit description initial state pre_en [2] prescaler control 0 = disable 1 = enable 0 pre_val [1:0] prescaler value 00 = 1/1 01 = 1/2 10 = 1/4 11 = 1/8 note: ms_sclk must be less than 20mhz 00 fifo interrupt control (msfintcon) register register address r/w description reset value msfintcon 0x46100004 r/w fifo interrupt control 0x0 msintcon bit description initial state fifo_inten [0] fifo states, which are receive buffer full (rbf), receive buffer empty (rbf), transmit buffer full (tbf) and transmit buffer empty (tbf) request interrupt or do not. 0 = only for xint 1 = enables interrupt request according to fifo states note: xint means internal conditions, which are detecting protocol end interrupt (int_p_end), serial interface interrupt (int_sif), tx/ rx request interrupt (int_tr), and insertion interrupt (int_ins). 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor memory stick 32-5 transfer protocol command (tp_cmd) register register address r/w description reset value tp_cmd 0x46108000 r/w transfer pr otocol command register 0x0000 msintcon bit description initial state tpc [15:12] transfer protocol command 0x2 = read page data 0xd = write page data 0x8 = set read/ write register address 0xe = set command 0x7 = get interrupt 0x4 = read register 0xb = write register others = reserved note: these bit fields can not be written while the int_p_end bit in intcon_sta register is ?0? . 0x0 reserved [11:10] reserved 00 dat_size [9:0] transferred data size 0x200 = read/ write page data command 0x4 = set read/ write register address 0x1 = set command/ get interrupt 0xx = any data size to read/ write register 0x00
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. memory stick S3C24A0 risc microprocessor 32-6 control and status (ctrlsta) register register address r/w description reset value ctrl_sta 0x46108004 r/w cont rol [15:8] and staus [7:0] register 0x050a msctrlsta bit description initial state rst [15] internal logic reset control 0 = clear reset 1 = reset 0 pws [14] power save mode control 0 = normal mode 1 = power save mode 0 sien [13] serial interface enable/ disable control 0 = disable 1 = enable 0 reserved [12] should be 0 (sbz) 0 nocrc [11] crc enable/ disable control 0 = enable 1 = disable 0 bsycnt [10:8] busy timeout counter timeout detecting time (ms_sclk cycles) = bsycnt x 4 + 2 example: bsycnt = 0x5, ms_sclk = 10mhz exceeding 2.2us (22 x 0.1) causes a rdy timeout error. 0x5 int_sta (read only) [7] interrupt status 0 = not generated interrupt condition 1 = generated interrupt condition 0 drq_sta (read only) [6] dma request status 0 = not requested dma 1 = requested dma 0 reserved [5:4] reserved 00 rbe_sta (read only) [3] receive buffer (fifo) empty status 0 = not empty 1 = empty 1 rbf_sta (read only) [2] receive buffer (fifo) full status 0 = not full 1 = full 0 tbe_sta (read only) [1] transmit buffer (fifo) empty status 0 = not empty 1 = empty 1 tbf_sta (read only) [0] transmit buffer (fifo) full status 0 = not full 1 = full 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor memory stick 32-7 data fifo (dat_fifo) register memory stick host controller has two 16-byte fifo for the tx and rx mode. transmit and receive fifo access is performed through same fifo entry: the address fifoenty is 0x46108008. register address r/w description reset value dat_fifo 0x46108008 r/w tx/ rx fifo (buffer) register 0x0000 msfifo bit description initial state fifoentry [15:0] transmit/ receive data for memory stick 0x0000
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. memory stick S3C24A0 risc microprocessor 32-8 interrupt control and status (intctrlsta) register register address r/w description reset value intctrl_sta 0x4610800c r/w interrupt control [15:8] and staus [7:0] register 0x0080 msintctrlsta bit description initial state int_en [15] internal enable/ disable control 0 = disable 1 = enable 0 reseved [14] reseved 0 ins_inten [13] insertion interrupt enable/ disable control 0 = disable 1 = enable 0 reserved [12:8] reserved 0x00 int_p_end (read only) [7] protocol end interrupt status 0 = in progress 1 = complete 1 int_sif (read only) [6] serial interface receive interrupt status (from memory stick) 0 = no interrupt 1 = receive interrupt 0 reseved [5] reseved 0 int_ins (read only) [4] insertion interrupt status 0 = no insertion 1 = insertion 0 reserved [3:2] reserved 00 int_crc (read only) [1] crc error interrupt status 0 = no crc error 1 = occurred crc error 0 int_toe (read only) [0] busy timeout error interrupt status 0 = no timeout error 1 = occurred timeout error 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor memory stick 32-9 ins port control (inscon) register register address r/w description reset value ins_con 0x46108010 r/w ins port control register 0x0000 msinscon bit description initial state reserved [15:13] reserved 000 ins_en [12] ins port enable/ disable control 0 = disable 1 = enable 0 reserved [11:5] reserved 0x00 ins_sta [4] ins port status 0 = high (no insertion) 1 = low (insertion) 0 reserved [3:0] reserved 0x0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. memory stick S3C24A0 risc microprocessor 32-10 auto command/ pol control (acmd_con) register register address r/w description reset value acmd_con 0x46108014 r/w auto command and polaity control register 0x0000 msacmdcon bit description initial state atpc_en [15] auto command operation enable/ disable control 0 = disable 1 = enable 0 pol [14] loading polarity control of the serial data input 0 = rising edge 1 = falling edge 0 reserved [13:0] reserved 0x00 auto transfer protocol command (atp_cmd) register register address r/w description reset value atp_cmd 0x46108018 r/w auto transfe r protocol command register 0x7001 msacmd bit description initial state atpc [15:12] set transfer protocol command (tpc) to be automatically executed. 0x7 reserved [11:10] reserved 0x0 adat_size [9:0] set the size of data which is transferred. 0x01
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-1 clock & power management overview the clock & power management unit consists of 3 parts; system clock control, usb clock control, and system power-management control. the system clock control logic in S3C24A0 can generat e the required system clock signals, armclk for cpu, hclk for the ahb-bus peripherals, and pclk for the apb-bus peripherals. there are two plls in S3C24A0. one is for armclk, hclk, and pclk, and the other is for t he usb, irda and camera interface. the clock control- logic can make slow clock without pll and connect/disconnect the clock to each peripheral block by software, which will reduce t he power consumption. in the power control logic, S3C24A0 has va rious power management schemes to keep optimal power consumption for a given task. the power management in s3c 24a0 consists of four modes: general clock gating (normal) mode, idle mode, stop mode, and sleep mode. general clock gating mode is used to control the on/off of clocks for internal peripherals in S3C24A0. the user can optimize the power cons umption of S3C24A0 using this general clock gating mode by supplying clocks for peripherals that are necessary for a certain application. for example, if a timer is not needed, the user can disconnect the clock to the timer to reduce power. idle mode disconnects the armclk only to cpu core while it supplies the clock to all peripherals. by using idle mode, the power consumption due to cpu core can be reduced. stop mode freezes all clocks to the cpu as well as per ipherals by disabling plls . the power consumption is only due to the leakage current in S3C24A0. sleep mode is intended to disconnect the internal pow er. so, the power consumption due to cpu and the internal logic except the wake-up logic will be ze ro in the sleep mode. in order to use the sleep mode two independent power sources are needed. one of the two power sources supplies the power for the wake-up logic. the other one supplies the other internal logic includi ng cpu, and should be controlled in order to be turned on/off. in sleep mode, the second power supply source for the cpu and internal logic will be turned off. a detailed description of the power-saving modes such as the entering sequence to the specific power-down mode or the wake-up sequence from a power-down mode is given in the following power management section.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-2 function description clock generation overview figure 33-1 shows the block diagram of the clock generation module. the main clock source comes from an external crystal (xsxtin) or external clock (xsextclk). the clock generator consists of two plls (phase- locked-loop) which generate the high-fr equency clock signals required in S3C24A0. xsxtin xsextclk xgrefclksel[1] mpll (m_m/ p/ s) extclkdiv 0 clkdivn (h/ p/ m) clockidle hclk pclk mpegclk armclk xsxtin xsextclk xgrefclksel[0] upll (u_m/ p/ s) 0 0 clkdivn (c) usbclk irdaclk camclk mpll_clk upll_clk 1/2 1/2 figure 33-1. clock generator block diagram clock source selection table 33-1 shows the relationship between the combination of mode contro l pins xgrefclksel[1:0] and the selection of source clock for S3C24A0. (see the figure 33-1.) table33-1. clock source selection for the internal plls and clock generation logic xgrefclksel[1:0] (refer to pin description) main clock source (mpll and external clock) usb clock source (upll and external clock) 00 xsxtin xsxtin 01 xsxtin xsextclk 10 xsextclk xsxtin 11 xsextclk xsextclk notes. 1. although the mpll/upll starts just after a reset, the mpll output (mpll_clk) isn't used as the system clock until the s/w writes valid settings to the mpllcon / upllcon regist er. before this valid setting, the clock from xsxtin or xsextclk source will be used as the system clock directly. even if the user wants to maintain the default value of mpllcon / upllcon register, the user should write the same value into mpllcon / upllcon register. 2. mpll generates the clock source for armclk, hclk, pclk and upll generates clock source for usbclk, irdaclk and camclk.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-3 pll (phase-locked-loop) the pll (phase-locked loop) frequency synthesizer is constr ucted in cmos on single monolithic structure. the pll provides frequency multip lication capabilities the output clock fr equency mpll_clk is re lated to the input clock frequency fin by the following equation: fout (mpll_clk or upll_clk) = (m * fin) / (p * 2 s ) where, m = m (the value for main divider)+ 8, p = p(the value for pre-divider p) + 2 where, fout is the output clock frequency. fin the input frequency. m, p and s are the values for programmable dividers (see the register description). the pll consis ts of a phase/frequency detector (pfd), a charge pump, an off-chip loop filter, a voltage controlled oscillator (v co), a 6 bit pre-divider, an 8bit main divider and 2-bit post scaler and shown in fig.33-2 the upll within the clock generator is same as the mpll in every aspect. to ensure the proper operation of the internal plls, we recommend the following pll value-sets(refer to table 33-7). if the user requires other range of pll set- values, please contact one of sec application engineers. pre- divider(p) pfd charge pump vco main divider(m) post scaler(s) off-chip loop filter fin fout figure 33-2. pll (phase-locked loop) block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-4 usual conditions for pll & clock generator table 33-2. recommended operation conditions characteristics min typ max unit supply voltage differential -0.1 0.1 v external loop filter capacitance 1.7 nf operating temperature -40 85 c table 33-3. dc electrical characteristics characteristics symbol min typ max unit operating voltage avdd12d/avdd12a 1.14 1.20 1.26 v dynamic current l dd 3ma power down current l pd tbd a table 33-4. ac electrical characteristics characteristics symbol min typ max unit input frequency f in 10 40 mhz output clock frequency f out 50 300 mhz vco output frequency f vco 100 300 mhz input clock duty cycle t id 40 50 60 % input glitch pulse width t igp 1ns jitter, cycle to cycle t jcc 200 200 ps clock control logic the clock control logic determines the clock source to be used, i.e., the pll clock(mpll_clk) or the direct external clock ( xsxtin or xsextclk ). when pll is c onfigured to a new frequency value, the clock control logic disables the armclk until the pll output is stabilized during the pll locking time. the clock control logic is also activated at power-on reset and waked-up from power-down mode. pll lock time the lock time is the minimum time required for pll out put stabilization. the lock time should be a minimum of 300us. after reset and wake-up from stop and sleep mode, re spectively, the lock-time is inserted automatically by the internal logic with lock time count register. the automatically inserted lock time is calculated as follows; t_lock (the pll lock time by h/w logic) = (1/ fin) x n where, n = m_ltime for mpll,u_ltime for upll, refer to the register description
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-5 power-on reset (xsresetn) figure 33-3 shows the clock behavior during the power -on reset sequence. the crystal oscillator begins oscillation within several milliseconds after the power source supplies enough power-level to the S3C24A0. internal plls (mpll and upll) also begins the frequency locking based on power-on-reset frequency-setting value. xsresetn signal should be released after the fully settle-down of the power-level. for the proper system operation, the S3C24A0 requires a hazard-free system clock (armclk, hclk and pclk) when the system reset is released (xsresetn). however, the pll is commonly k nown to be unstable after power-on reset, so fin (the direct external clock source, xsxtin or xsextc lk depending on the xgrefclksel[1:0] pin status) is fed directly to armclk instead of the mpll_clk (pll output) before the s/w newly configures the mpllcon register. even if the user wants to use the default val ue of mpllcon register, user should write the same value into mpllcon register by s/w after the release of the system reset. the pll begins the lockup sequence toward the new frequency only after the s/w configures the pll with a new frequency-value. armclk is configured to be pll output (mpll_clk) immediately after lock time. the user should be aware that the crys tal oscillator settle-down time is not explicitly added by the hardware during the power-up sequence. the S3C24A0 a ssumes that the crystal oscillation is settled during the power-supply settle-down period. however, to ensure the proper operat ion during wake-up from the stop mode, the S3C24A0 explicitly adds the crystal osc illator settle-down time (the wait-time can be programmed using the xtalwset registers) after wake-up from the stop mode. for the usb, irda and camera interface device clocks, the output of upll clock is directly fed to those devices. the logic operates by xsextclk or xsxtin xsresetn xsextclk or xsxtin vco output power clock disable lock time pll is configured by s/w first time. vco is adapted to new clock frequency. armclk armclk is new frequency figure 33-3. power-on reset sequence
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-6 change pll settings in normal operation during the operation of S3C24A0 in normal mode, if the user wants to change the frequency by writing the pms value, the pll lock time is automatically inserted. during the lock time, the clock is not supplied to the internal blocks in S3C24A0. the timing diagram is as follow. mpll_clk pms setting pll lock-time armclk it changes to new pll clock after lock time automatically figure 33-4. the case that changes slow clock by setting pms value note : changing pms value can cause a problem in lcd display. in the S3C24A0, the lcd screen-refresh timing is dependent on the hclk (hclk clock is also dependent on the mpll clock output). armclk, hclk, pclk, mpegclk and camclk control the armclk is used for arm926ej-s core, the main cpu of the S3C24A0. the hclk is the reference clock for internal ahb bus and peripherals such as the memory controller, the interrupt controller, the modem interface, lcd controller, the dma, usb host block, system controller, power down controller and etc. the pclk is used for internal apb bus and peripherals such as wdt, iis, i2c, pwm timer, and mmc interface, adc, uart, gpio, rtc and spi etc. mpegclk is used for mpeg4 h/w accelerator block such as dct, me, mc block. camclk is used for camera interface block. the following table shows the clock division ratios bet ween armclk, hlck and pclk. this ratio is determined by hdiv and pdiv bits of clkdivn control register. hclkdiv[1:0] pclkdiv armclk hclk pclk division ratio 00 0 armclk armclk armclk 1 : 1 : 1 (default) 00 1 armclk armclk armclk / 2 1 : 1 : 2 01 0 armclk armclk / 2 armclk / 2 1 : 2 : 2 01 1 armclk armclk / 2 armclk / 4 1 : 2 : 4 10 0 armclk armclk / 4 armclk / 4 1 : 4 : 4 10 1 armclk armclk / 4 armclk / 8 1 : 4 : 8
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-7 mpegclk and camclk frequency are determined by mpegcl kdiv[3:0] and camclkdiv[3:0] bits of clkdivn control register. mpeg or camclkdiv[3:0] mpegclk camclk 0 hclk upll_clk / 2 1~15 hclk / ( 2 x mpegclkdiv ) upll_clk / (camclkdiv + 1 ) * 2 the mpegclk and the camclk frequency are changed whenever the source clock frequency is changed. uclk (usb clock) control usb host interface and usb device interface needs 48mhz fixed-frequency clock. in the S3C24A0, the usb dedicated pll (upll) generates 96mhz and divided by two for usb block. upll will be turned off during stop and sleep mode automatically. also, upll will be generated clo ck to usbclk, irdaclk, camclk after exiting stop and sleep mode if usbon, irdaclkon and camc lkon bits are enabled in clkcon register. condition uclk state upll state after reset upll output on after configuring upll during pll lock time: low after pll lock time: upll output on upll is turned off by u_plloff bit in clksrc register no clock off upll is turned on by u_plloff bit in clksrc register upll output on note: upll_clk (upll output) is 98mhz. usbclk is obtained by dividing by two of upll_clk, i.e. upll_clk/2.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-8 power management the power management block controls the system clocks by software for the reducti on of power consumption in S3C24A0. these schemes are related to pll, clock control logic(armclk,hclk,pclk) and wake-up signal. the figure 33-5 depicts the clock distribution of S3C24A0. S3C24A0 has four power-down modes. the follo wing section describes each power management mode. pll (main & usb) fin mpll_out upll_out clock generation (on/ off control) system configuration registers system configuration registers vpost mpeg4me mpeg4dctq vlx mpeg4if lcd camif vpostif usb host usb irda cam ac97 pwm timer uart0 uart1 spi i2c i2s gpio usb device memory stick sd adc key pad mpegclk hclk pclk upllclk armclk arm926-ej figure 33-5. the clock distribution block diagram
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-9 power saving modes general clock gating mode in general clock gating mode, the on/off clock gating of the individual clock source of each ip block is performed by controlling of each corresponding clock s ource enable bit. the clock gating is applied instantly whenever the corresponding bit (or bits) is changed. (in general, these bits are set or cleared by the main cpu.) idle mode in idle mode, the clock to cpu core is stopped. the idle mode is activated just after the execution of the str instruction that enables the idle mode bit. the idle mode bit should be cleared by software after the wake-up from the idle state because it is not cleared automatically, and the h/w logic only detects the low-to-high triggering of the idle mode bit. stop mode in stop mode, all clocks are stopped for minimum power c onsumption. therefore, the pll and oscillator circuit are also stopped. the stop mode is activated after the execution of the str instruction that enables the stop mode bit. the stop mode bit should be cleared by software after the wake-up from the stop state because it is not cleared automatically, and the h/w logic only detects the low-to-high triggering of the stop mode bit. to exit from stop mode, external interrupt, rtc al arm, touch screen pen-down int, modem int, xsresetn or xswresetn has to be activated. during the wake- up sequences, the crystal o scillator and pll may begin to operate. the crystal-oscillator settle-down-time and t he pll locking-time is required to provide stabilized armclk. those time-waits are automatically inserted by the hardware of the S3C24A0. during these time-waits, the clock is not supplied to the internal logic circuitry. stop mode entering sequence is 1) set the stop mode bit by software. 2) set the sdram in self-refresh mode to preserve its contents (the power-manager of S3C24A0 requests the entering of the self-refresh state to the sdram controller of S3C24A0 and it issues the self-refresh command.) 3) after receiving the self-refresh acknow ledge, disables the x-tal and pll oscillation. stop mode exiting sequence is 1) enable x-tal oscillator if it is used, and wait the osc settle down (around 1ms). 2) after the oscillator settle-down, the system clock is fed using the pll input clock and also enable the plls and waits the pll locking time. 3) switching the clock source, now the pll is the clock source. 4) the sdram controller releases the self-refresh mode just before the S3C24A0 access the sdram. notes: 1. dram has to be in self-refresh mode during stop and sleep mode to retain valid memory data. 2. lcd must be stopped before stop and sleep mode, because dram can't be accessed when it is in self-refresh mode.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-10 xsxtin or xsextclk wake-up vco output clock disable armclk stop mode is initiated. lock time a xtalwset figure 33-6. entering stop mode and exiting stop mode (wake-up) sleep mode in the sleep mode, all the clock sources are off and also t he internal logic-power is not supplied except for the wake-up logic circuitry. in this mode, the static power-dissipation of internal logic can be minimized. sleep mode entering sequence is as follows. 1) one of the sleep mode entering events is trigger ed by the system software or by the hardware. 2) set the sdram in self-refresh mode to preserve its contents (the power-manager of S3C24A0 requests the entering of the self-refresh state to the sdram controller of S3C24A0 and it issues the self-refresh command.). 3) after receiving the self-refresh a cknowledge, disables the x-tal and p ll oscillation and also disables the external power source for the internal logic by asserting xgpwroffn signal to low state. xgpwroffn signal is the regulator-disable control signal for the internal-logic power-source. sleep mode exiting sequenc e is as follows. 1) enable external power source by deactivation of the xgpwroffn signal and wait power settle down time (around 6ms, it is programmable by a register in the gpio block). 2) release the system reset (synchronously, relatively to the system clock) after the power supply is stabilized (see the gpio descriptions). 3) the sdram controller releases the self-refresh mode just before the S3C24A0 access the sdram.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-11 power mode state diagram figure 33-7 show that power saving mode state and entering or exiting condition. in general, the S3C24A0 issues the entering conditions. normal (general clock gating mode) idle sleep stop cmd cmd nbatflt nbatflt cmd or nbatflt one of wakeup source reset or restricted wakeup evants. one of wakeup source figure 33-7. power mode state diagram wake-up event when the S3C24A0 wakes up from the stop mode or the sleep mode by an external interrupt, a rtc alarm interrupt and other interrupts, the pll is turned on automatically. however, the clock supply scheme is quite different. the initial-state of the S3C24A0 after wa ke-up from the sleep mode is al most the same as the power- on-reset state except for the contents of the external dram is preserved. in contrast, the S3C24A0 automatically recovers the previous working state after wake-up from the stop mode. the following table shows the states of plls and inte rnal clocks after wake-ups from the powe r-saving modes. table 33-5. the status of pll and armclk after wake-up mode before wake-up pll on/off after wake up armclk after wake up and before the lock time armclk after the lock time by internal logic idle unchanged pll output pll output stop off on no clock pll output sleep off on external clock external clock output port state in stop and sleep mode refer to pin assignment table * in product overview chapter.
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-12 power saving mode entering/exiting condition table 33-6 shows that power saving mode state and entering or exiting condition. table 33-6. power saving mode entering/exiting condition power saving mode entering exiting normal disable the clkcon bit for each ip block enable the clkcon bit for each ip block idle enable the clockidle bit of clkcon register 1) external int[9:0] 2) rtc alarm int 3) touch screen pen-down int 4) modem int 5) xswresetn 6) xsresetn stop enable the clockstop bit of clkcon register 1) external int[9:0] 2) rtc alarm int 3) touch screen pen-down int 4) modem int 5) xswresetn 6) xsresetn sleep write ?0xa3? to the sleep_code[7:0] bits of pwrman register 1) external int[9:0] 2) rtc alarm int 3) xswresetn 4) xsresetn sleep when the xgbatflt port goes to low 1) external int: gpio[1:0] 2) xswresetn 3) xsresetn notes: 1. the wake-up event sources for the sleep mode due to the xgbatflt are limited as in the above table. 2. entering to the sleep mode by the xgbatflt is programmable, 1) the xgbatflt can be forwarded as an fiq 2) the xgbatflt can be used as t he entering event for the sleep mode 3) the xgbatflt can be ignored. reset definition reset definition xsresetn this is the cold reset. the internal state (include registers) of the S3C24A0 will be initialized when xsresetn is activated. the xs resetn is a non-maskable signal except for the case when the xgbatfltn is in the active state (low). the contents of the sdram will not be pr eserved when the xs resetn is applied. xswresetn, softreset the xswresetn and the soft-reset reset the system except rtc, clock generator, power management module and memory controller (preserves sdram data)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-13 clock generator & power management special register lock time count register (locktime) register address r/w description reset value locktime 0x40000000 r/w pll lock ti me count regist er 0x0fff_0fff locktime bit description initial state u_ltime [27:16] upll lock time count (generally 300us) 0xfff m_ltime [11:0] mpll lock time count (generally 300us) 0xfff pll locking time locking time = (1/fin) * (u_ltime or m_ltime * 16) x-tal oscillation wait register (xtalwset) register address r/w description reset value xtalwset 0x40000004 r/w crystal oscillat or settle-down wait time 0x5000_5000 xtalwset bit description initial state u_oscwait [31:16] upll crystal osc illator settle-down wait time 0x5000 m_oscwait [15:0] mpll crystal oscillator settle-down wait time 0x5000 x-tal settle-down wait time x-tal settle-down time = tcrystal_clock * (u_oscwait or m_oscwait)
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-14 pll control register (mpllcon, upllcon) pll value selection guide 1. mpll or upll = (m * fin) / (p * 2 s ), where: m = (mdiv + 8), p = (pdiv + 2), s = sdiv 2. fin/(25*p) < 16.7e6/m < fin/(10*p) 3. 0.7 < 6.48/sqrt(m) < 1.8 4. (fin/p)*m < 330e6 register address r/w description reset value mpllcon 0x40000010 r/w mpll configuration register 0x0004_8021 upllcon 0x40000014 r/w upll configuration register 0x0003_0021 m/u pllcon bit description initial state mdiv [19:12] main divider control ( m value ) 0x48 / 0x30 pdiv [9:4] pre-divider control ( p value ) 0x02 / 0x02 sdiv [1:0] post divider control ( s value ) 0x1 / 0x1 to ensure the proper operation of the internal plls, we recommend the following pll value-sets. if the user requires other range of pll set-values, please contact one of sec application engineers. table 33-7 pll value selection table input frequency output frequency (mhz) mdiv pdiv sdiv 12.00mhz 84 34 (0x22) 1 1 12.00mhz 90 37 (0x25) 1 1 12.00mhz 96 56 (0x38) 2 1 12.00mhz 102 43 (0x2b) 1 1 12.00mhz 112.5 67 (0x43) 2 1 12.00mhz 118 51 (0x33) 1 1 12.00mhz 124 54 (0x36) 1 1 12.00mhz 132 58 (0x3a) 1 1 12.00mhz 136 60 (0x3c) 1 1 12.00mhz 176 36 (0x24) 1 0 12.00mhz 177 51 (0x33) 2 0 12.00mhz 180 37 (0x25) 1 0 12.00mhz 186 54 (0x36) 2 0 12.00mhz 192 56 (0x38) 2 0 12.00mhz 200 42 (0x2a) 1 0 12.00mhz 204 60 (0x3c) 2 0
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-15 clock control register (clkcon) register address r/w description reset value clkcon 0x40000020 r/w clock generator control register 0x03fffff0 clkcon bit description initial state vlxclkon [29] controls hclk into vlx block 0: disable 1: enable 1 vpostclkon [28] controls mpegclk into vpost block 0: disable 1: enable 1 reserved [27] reserved mpegdctqclkon [26] controls mpegclk into mpegdctq block 0: disable 1: enable 1 vpostifclkon [25] controls hclk into vpost block (ahb bus side) 0: disable 1: enable 1 mpegifclkon [24] controls hclk into mpeg ahb interface 0: disable 1: enable 1 camclkon [23] controls upll_clk into cam block 0: disable 1: enable 1 lcdclkon [22] controls hclk into lcd block 0: disable 1: enable 1 camifclkon [21] controls hclk into camera interface block 0: disable 1: enable 1 mpegmeclkon [20] controls mpeg4clk into mpeg me block 0: disable 1: enable 1 keypadclkon [19] controls pclk into key pad block 0: disable 1: enable 1 adcclkon [18] controls pclk into adc block 0: disable 1: enable 1 sdclkon [17] controls pclk into sd block 0: disable 1: enable 1 msclkon [16] controls pclk into memory stick block 0: disable 1: enable 1 usbdeviceclkon [15] controls pclk into usb device block 0: disable 1: enable 1 gpioclkon [14] controls pclk into gpio block 0: disable 1: enable 1 iisclkon [13] controls pclk into iis block 0: disable 1: enable 1 iicclkon [12] controls pclk into iic block 0: disable 1: enable 1 spiclkon [11] controls pclk into spi block 0: disable 1: enable 1
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-16 clkcon bit description initial state uart1clkon [10] controls pclk into uart1 block 0: disable 1: enable 1 uart0clkon [9] controls pclk into uart0 block 0: disable 1: enable 1 pwmtimerclkon [8] controls pclk into pwmtimer block 0: disable 1: enable 1 usbhostclkon [7] controls hclk into usb host block 0: disable 1: enable 1 ac97clkon [6] controls pclk into ac97 block 0: disable 1: enable 1 reserved [5] reserved(should be zero) 0 irdaclkon [4] controls upll_clk into irda block 0: disable 1: enable 1 reserved [3] reserved 0 clockidle [2] enters idle mode. this bit is not cleared automatically. 0: disable 1: transition to idle mode 0 clkmonon [1] hclk monitor enable 0: disable 1: enable 0 clockstop [0] enters stop mode. this bit is not cleared automatically. 0: disable 1: transition to stop mode 0 clock source control register (clksrc) register address r/w description reset value clksrc 0x40000024 r/w clock source control register. 0x00000004 clksrc bit description initial state onosc_en [8] crystal oscillator enable control during the stop mode 0: disable 1: enable 0 u_plloff [7] upll on/off control 0: on 1: off 0 reserved [6] reserved 0 m_plloff [5] mpll on/off control 0: on 1: off 0 selextclk [4] select external clock source for armclk/hclk/pclk 0: mpll_clk 1: external clock 0 reserved [3] reserved 0 extclkdiv [2:0] external clock division factor 000: no division001 ~ 110: divided by (2*extclkdiv) 111: reserved for the S3C24A0 test 4
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. S3C24A0 risc microprocessor clock & power management 33-17 clock divider control register (clkdivn) register address r/w description reset value clkdivn 0x40000028 r/w clock divider control register 0x0000_0300 clkdivn bit description initial state camclkdiv [11:8] camclk division factor 0x5 mpegclkdiv [7:4] mpegclk division factor 0 hclkdiv [2:1] hclk division factor 00: armclk: hclk = 1:1 01: armclk: hclk = 1:2 10: armclk: hclk = 1:3 11: armclk: hclk = 1:4 0 pclkdiv [0] 0: pclk has the clock same as the hclk 1: pclk has the clock same as the hclk/2 0 power management control register (pwrman) register address r/w description reset value pwrman 0x40000030 r/w power management register 0x0000_1000 pwrman bit description initial state use_wfi [12] use the wfi (wait for interrupt) instruction before enter into stop and sleep mode. if this bit is set, the power management block checks the internal signal (standbywfi), so wif instruction must be added by software. 0: not use 1: use the wfi 1 mask_modem [11] baseband modem wakeup mask setting register 0: unmask 1: mask 0 cnfg_bf [10:9] battery fault handling configuration setting register 00: emergency sleep 01: fiq 10: ignore 11: reserved 0x0 mask_ts [8] touch screen wakeup mask setting register 0: unmask 1: mask 0 sleep_code [7:0] sleep mode setting code - note: 1. sleep_code is 0xa3. when this register was set wi th the value of 0xxxxx_xxa3 the sleep mode is activated. 2. when using the wfi instruction in the arm926ej-s core by setting the use_wfi bit, the entering sequence of power-saving mode is as follows, a. set the clockstop bit in clkcon register or writ e sleep code to sleep_code bits in pwrman register. b. execute the wfi instruction
bsw rv0.1-0417-n01 preliminary product information describes products that are in development, for which full characterization data and associated errata are not yet available. specifications and information herein are subject to change without notice. clock & power management S3C24A0 risc microprocessor 33-18 softreset control register (softreset) register address r/w description reset value softreset 0x40000038 r/w software reset control register - softreset bit description initial state soft reset [7:0] software controlled reset setting code - note: softreset command is 0xa3. when this register was set wi th the value of 0xxxxx_xxa3 the soft-reset is activated.

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